International Journal of Engineering and Technology

Reliable on-board state estimation demands high sensor sampling rate so as to update the CPU with present state of the robot fast enough. Since on-board CPUs often have limited computational capacity, a robot must be designed to use this resource efficiently. Current protocols force the CPUs to spend a considerable amount of time fetching sensor data, which delays the state estimation and affects crucial operations like planning and execution of control algorithms. This problem becomes predominant in high-speed robots, where state estimation needs to be extremely fast and accurate. This research, therefore, presents an enhanced communication protocol, aimed at minimizing the CPU intervention time required for fetching sensor data. The work also proposes deployment of the said communication protocol on a hardware accelerator for a drastic reduction in the CPU intervention time. The design was first simulated using Xilinx ISE Design Suite and subsequently implemented on a PSoC 5LP for hardware experimentation. The performance of serial and parallel implementations of the proposed communication protocol was analyzed comparatively against that of the standard I2C protocol.