Parameter Fluctuations in Multiple Patterned Deca-nm Scaled CMOS Structures

Klaus T. Kallis; John T. Horstmann; H.L. Fiedler

doi:10.4028/www.scientific.net/JNanoR.17.157

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HomeJournal of Nano ResearchJournal of Nano Research Vol. 17Parameter Fluctuations in Multiple Patterned...

Parameter Fluctuations in Multiple Patterned Deca-nm Scaled CMOS Structures

Abstract:

Multiple Patterning Seems to Be One of the Most Promising Solutions for the Gap between the 193 Nm Immersion Lithography and the 13.5 Nm EUV Lithography for Industrial Manufacturing of Ultra Large Scaled Integrated CMOS Circuits [1]. the Used Techniques in this Paper Lead to an Excellent Homogeneity and Uniformity of the Channel Length and Width which Enables a Fundamental Statistical Analysis of the Electrical Transistor Parameters. the Process Flow Has Been Optimized to Minimize the Active Channel Area and to Achieve a Sufficient Yield for a Trustworthy Statistical Analysis. while the Channel Length Is Defined by a Single Deposition- and Etchback Technique the Active Area Is Defined by a Composition of Multiple Spacers that Lead to a Diffusion Stop Barrier. the Statistical Analysis of these Devices Shows Dramatically Increasing Fluctuations of the Threshold Voltage if the Device Dimensions Are Decreased.

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Periodical:

Journal of Nano Research (Volume 17)

Pages:

157-163

DOI:

https://doi.org/10.4028/www.scientific.net/JNanoR.17.157

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Online since:

February 2012

Authors:

Klaus T. Kallis, John T. Horstmann, H.L. Fiedler

Keywords:

CMOS Technology, Device Parameter Fluctuations, Double Patterning, Matching, Scaling, Sub-50 Nm-MOS-Transistors

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