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Article

VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT

1
Department of Electronic Engineering, Chung Yuan Christian University, Taoyuan City 320317, Taiwan
2
Department of Electrical Engineering, Ming Chi University of Technology, New Taipei City 243303, Taiwan
3
School of Physical Educational College, Jiaying University, Meizhou 514000, China
4
Department of Information Systems and Computer Science, Ateneo de Manila University, Quezon City 1108, Philippines
5
Department of Microelectronics, College of Physics and Information Engineering, Fuzhou University, Fuzhou 350025, China
6
Department of Information Management, Chung Yuan Christian University, Taoyuan City 320317, Taiwan
*
Authors to whom correspondence should be addressed.
These authors contributed equally to this work.
Sensors 2023, 23(3), 1573; https://doi.org/10.3390/s23031573
Submission received: 13 December 2022 / Revised: 20 January 2023 / Accepted: 26 January 2023 / Published: 1 February 2023
(This article belongs to the Special Issue Sensors and Signal Processing for Biomedical Application)

Abstract

:
It has always been a major issue for a hospital to acquire real-time information about a patient in emergency situations. Because of this, this research presents a novel high-compression-ratio and real-time-process image compression very-large-scale integration (VLSI) design for image sensors in the Internet of Things (IoT). The design consists of a YEF transform, color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, prediction, quantization, and Golomb–Rice coding. By using machine learning, different BTC parameters are trained to achieve the optimal solution given the parameters. Two optimal reconstruction values and bitmaps for each 4 × 4 block are achieved. An image is divided into 4 × 4 blocks by BTC for numerical conversion and removing inter-pixel redundancy. The sub-sampling, prediction, and quantization steps are performed to reduce redundant information. Finally, the value with a high probability will be coded using Golomb–Rice coding. The proposed algorithm has a higher compression ratio than traditional BTC-based image compression algorithms. Moreover, this research also proposes a real-time image compression chip design based on low-complexity and pipelined architecture by using TSMC 0.18 μm CMOS technology. The operating frequency of the chip can achieve 100 MHz. The core area and the number of logic gates are 598,880 μm2 and 56.3 K, respectively. In addition, this design achieves 50 frames per second, which is suitable for real-time CMOS image sensor compression.

1. Introduction

In recent years, people have obtained various information from digital images and videos, whether in the fields of entertainment, education, medicine, and traffic monitoring. For example, in the medical field, the problem of a high patient ratio is very difficult. Overcrowding in emergency departments is a serious global healthcare issue [1]. It has always been difficult for hospitals to obtain real-time information on their patients’ critical circumstances. Emerging Internet of Things (IoT) frameworks enable us to create tiny devices capable of processing, sensing, and communicating [2,3]. Signal processing and signal collection frequently use image sensors. Image sensor arrays, including CMOS image sensors for visible light and the thermal imaging sensor, have been used more and more in a variety of applications due to their constant performance improvement and cost reduction [4]. A growing number of buildings and huge surroundings are being monitored for pollution using image sensors, such as crop growth records, surveillance of road traffic, border monitoring, and monitoring of forest fires. These applications require real-time and high-quality performance to process the captured data with high resolution. However, the increasingly large amount of data has caused a heavy burden on transmission. To achieve transmission and maintain image quality, it is imperative to combine compression techniques. Because of this, this study proposes an image compression hardware circuit architecture with a high compression ratio, high efficiency, and low complexity. It aims to address the challenging issue of IoT huge data transmission and lower the expense of sampling redundant data.
Image compression coding algorithms can be divided into lossless and lossy methods. Lossless image compressions have better image performance after decompression than lossy image compression. For example, Chen et al. [5,6] designed a VLSI architecture for wireless body sensor network systems for wireless sensor networks (WBSNs). This design includes a simplified data encoder which can reduce data information by lossless compression. Video sensor networks (VSNs) are used to transmit high-quality video with huge data information such as high-efficiency video coding (HEVC) [7]. However, high-quality lossless compression techniques are still limited for reducing huge data. In addition, lossy image compression algorithms have higher compression rates than lossless image compression algorithms. In the prior art, common image compression algorithms include JPEG [8,9,10,11,12] and block truncation coding (BTC) [13,14,15,16,17]. For the development of JPEG technology, JPEG-CHE [10] decompresses precise data via compression history estimation (CHE), which is usually discarded after decompression. Ramesh et al. [11] proposed a state-of-the-art method based on JPEG XS [12] to directly compress the Bayer color filter array (CFA) data. JPEG technology’s complexity and compression ratio, meanwhile, are still not perfect. Delp et al. [13] developed block truncation coding (BTC), a straightforward method with excellent compression rates, to reduce algorithm complexity. BTC is a suitable algorithm for hardware implementation. Based on hardware design, Bo et al. [14] proposed an efficient image compression algorithm named Microshift. Hardware friendliness in design allows it to be implemented on FPGA and have high image quality. It adopts down-sampling to divide an image into nine sub-images which are more suitable for compression. The first sub-image is compressed by lossless compression and the other eight sub-images are predicted by it. Microsoft has good quality with higher PSNR. However, it does not have a higher compression rate. Adaptive sampling block compressed sensing (ABCS) is an adaptive sampling method used to process smooth, texture, and edge regions [15]. Adaptive samples can improve the quality of different texture details. Li et al. [16] adopted ABCS for the Green Internet of Things (GIoT) with low power consumption. Sovannarith et al. [17] proposed a fuzzy adaptive sampling block compressed sensing (FABCS) which combined ABCS and a fuzzy logic system (FLS). This algorithm can be applied in wireless multimedia sensor network (WMSN) architecture and detect features to sample the base and feature layer. Then, the algorithm measures the compressed sensing and transmits it over to WMSN. The image can be reconstructed by FLS to adaptively adjust the sampling rate. The BTC algorithm substitutes the DCT and wavelet transform with two reconstruction values and splits the whole picture into non-overlapping blocks for computation. The BTC algorithm is suitable for hardware implementation by reducing complex calculations. According to the literature review, it is suggested that the lossy image compression technique is preferred for enhancing picture accuracy and it can be divided into four stages: conversion, prediction, quantization, and encoding. The formula of BTC is as shown in Equations (1) and (2):
x l = x _ σ q 16 q
x h = x _ + σ 16 q q
where the low reconstruction value is represented by x l , the high reconstruction value is represented by x h , and the number of pixels above average is represented by q . The average value and standard deviation of each 4 × 4 block are represented by x _ and σ , respectively.
In variable-length coding, the number of data occurrences can determine the code length. Data with a high probability of occurrence will be encoded into a shorter length. By contrast with a high probability of occurrence, data will be encoded into a longer length. The variable-length coding length is shorter than that of fixed-length encoding, which improves the compression rate. One of the most famous is the Huffman coding [18], which is widely cited in image compression technology. Huffman coding creates the shortest code based on a binary tree. The Golomb code [19] was invented by Solomon W. Golomb in 1960. It is another variable-length encoding that uses an adjustable parameter M to divide the input data into quotient and remainder. Although Huffman coding has a higher compression rate, it consumes a lot of time in calculations because it needs to calculate the entire image and count the probability before encoding. In addition, Huffman coding needs to store the code information for comparison during encoding and decoding. As a result, the hardware design requires additional memory as a code comparison table, which increases the area and cost. Chen et al. [20] proposed a chip design for lossless image compression for wireless capsule endoscopy. This proposal selects Golomb–Rice coding to reduce area and real-time processes in hardware design. The study presented ultimately aims to improve image compression technology and make contributions to IoT devices. And this allows on-chip integration with image sensors to fulfill the requirement of high-speed applications. For example, WNSs tend to transmit data information in real-time [21]. These are the innovations of this methodology:
  • Adaptive threshold is a new feature added by this research to image compression technology. Different BTC parameters are trained using machine learning to acquire the best possible parameter solution.
  • This study suggests a cutting-edge BTC with 4 × 4 block construction for numerical conversion technology, effectively eliminate pixel redundancy to reduce duplicate information and utilize quantization, prediction, and subsampling. It demonstrates the simplicity and efficiency of the suggested approach. Additionally, the suggested approach outperforms the conventional 4 × 4 block image compression technique based on BTC in terms of compression ratio. The figure of merit (FOM) has increased by roughly 33.79%, reaching 334.6391.
  • The innovation of this work is to realize a real-time image compression chip design based on low-complexity and pipelined architecture by using TSMC 0.18 μm CMOS technology. It can perform three-stage compression work at the same time. The final compression rate of the circuit architecture proposed in this proposal is as high as 50 frames per second. Experiments prove that it can be applied to real-time CMOS image sensor compression.
The layout of this study is as follows: The Materials and Methods for the compression method are presented in Section 2. The assessment techniques and experimental findings of compression technology and hardware use are mostly described and examined in Section 3. The study’s conclusions are discussed in Section 4. In Section 5, conclusions and outlooks are presented. This proposal aims to address the issue of large-scale transmission of image sensors in IoT by using BTC and Golomb–Rice coding to conduct image compression with high compression rate and low complexity, and to achieve high performance through pipeline circuit design.

2. The Proposed Lossy Image Compression Algorithm

Figure 1 depicts the flowchart of the compression method developed in this study. First, the original image in RGB color space is converted to YEF color space and is sampled in 4:2:0 format to the E and F color spaces afterward. Second, in order to determine the two ideal reconstruction values and bitmap for each 4 × 4 block, BTC training is then carried out. Third, the E and F color spaces are sampled in a 4:2:2 format. Fourth, the reconstructed values are subtracted to obtain the predicted symbol. Finally, Golomb–Rice coding is quantized based on the quantization table.

2.1. YEF Color Space Sampling

According to the literature review, changes in luminance are easier to observe by the human visual system than changes in chrominance. Image processing benefits from converting an image from its original RGB color space to luminance and chrominance space. The conversion formula of the color space from RGB to YEF is shown in Equation (3).
Y = R 4 + G 2 + B 4   E = R 8 G 4 + B 8 + 128   F = R 8 + G 8 B 4 + 128
The conversion formula of the YEF color space is relatively simple to divide the image into luminance and chrominance. It only needs some adders and shifters, which can make the hardware design easier to implement. It can also reduce the cost of the circuit area and the timing. For this reason, YEF color space is more suitable for this proposed image compression.
The distribution of pixels in the RGB color space is shown in Figure 2. Figure 3 shows the pixel distribution in the YEF color space. The range of pixel change in the RGB color space is absolutely wider than that of the YEF color space, because these three-color planes store the information of the chrominance and luminance. By contrast, the values of the adjacent pixels on the E and F spaces are concentrated and smooth. This indicates that color sampling, fused in E and F spaces, can be employed to save data storage. In addition, during the decompression process, nearby pixels may readily compute the loss value of color sampling. The Y space stores the luminance strength, which is important information about an image, thus it will not be sampled to avoid degradation of image quality.
The proposed study selects the 4:2:0 sampling format to sample E and F color space, which can achieve a higher compression rate. The 4:2:0 sampling is to discard half of the vertical and horizontal pixels of the image. Hence, there are many different 4:2:0 sampling positions. For different sampling positions, the image quality results are not the same. One is to consider whether E and F are sampled in the same position, and the other is whether E and F are sampled in the same vertical direction. This study takes the 4:2:0 sampling positions as shown in Figure 4.

2.2. BTC Algorithm and Threshold Optimization

The BTC algorithm [21] has a lower complexity than the traditional BTC or AMBTC algorithm, which can save hardware costs. In view of this, this research proposes a more advanced threshold optimization, the BTC algorithm. This method not only maintain the image compression rate, but also improves the image quality. A bitmap is binary information. The threshold in the traditional BTC algorithm is the average of the blocks utilized. The conversion formulas are shown in Equations (4) and (5):
B M i , j = { 1 , i f   X i , j > a v e r a g e   0 ,           o t h e r w i s e
where the current pixel value is X(i,j),and BM(i,j) is the result of binary from X(i,j).
R i , j = { a ,   i f   B M i , j = 0   b , i f   B M i , j = 1
where the decoded pixel value is R(i,j). The low and high reconstruction values are a and b, respectively.
When the current pixel value is greater than the average value, and the distance between the reconstructed value a and the current pixel value is less than the reconstructed value b, the current pixel value is considered to be the high reconstructed value b. However, the original pixel is closer to the low reconstructed value a. Because the decoded value of the pixel depends on the threshold, selecting an appropriate threshold for decompression is important. This method can effectively improve the PSNR of the image without affecting the compression rate. Therefore, the improved formula based on the research in [22] is shown in Equation (6):
B M i , j = { 1 , i f   X i , j a > X i , j b   0 , i f   X i , j a X i , j b }

2.3. BTC Training

The two reconstruction value procedures of BTC employed in this research are shown in Equations (7) and (8). The calculation of threshold optimization complexity is reduced, but without the standard deviation, it cannot maintain the high performance of image quality. In order to improve this problem, the variable parameters α1 and α2 will enable the algorithm to calculate the best reconstruction value to compensate for the image quality. The machine learning adjusts and trains the parameters α1 and α2, which are variable values from 0 to 1. Each cycle will increase by 0.25 and the current two reconstruction values are calculated for each iteration.
a = m i n + α 1 m e a n m i n
b = m a x α 2 m a x m e a n

2.4. Subsampling

Because the E and F color spaces are more concentrated on the adjacent pixel change, the reconstruction value of each 4 × 4 block after BTC training will be very similar. Therefore, sampling the reconstruction value in the E and F color spaces can effectively increase the compression rate. The sampling format adopts the 4:2:2 format as shown in Figure 5, and it is possible to only use half of the original data for the color spaces of E and F. Considering the real-time implementation of the hardware design, the 4 × 4 block bitmap that are discarded during the up-sampling is equal to the previous 4 × 4 block bitmap. The discarded reconstructed value will be replaced by the average of the adjacent values.

2.5. Prediction and Quantization

The prediction method used in this subsection is shown in Equation (9), which uses the difference between the two adjacent values as a prediction. Compared with the prediction method in the research in [23], it has a better performance of image quality since the prediction method used in this research will cause the edge pixels of the image to be discontinuous during decompression. However, the prediction method just needs the previous and current pixel values. It does not need to store the entire data for prediction.
d i f f = C u r r e n t   p i x e l P r e v i o u s   p i x e l
In order to make the encoding process beneficial, the range of the difference value −255~255 is quantized into 0~31, thereby shortening the code length during encoding and further improving the compression rate. The difference is usually small because of the characteristics of the similar distribution of adjacent pixels. This means that the probability of a small difference value is higher than a large difference value. Therefore, the smaller difference value will be quantized into a smaller range of encoding and decoding as shown in Table 1.

2.6. Golomb–Rice Coding

Golomb–Rice coding does not need to calculate the entire image, nor does it need an encoding table. The number of bits about the quotient and remainder is determined by the M value. In order to realize hardware circuits, Robert F. Rice proposed the use of Rice coding to limit the value of M to the power of 2. The detailed encoding steps are as follows:
Step 1: set the parameter M, which can determine the bit number of the remainder as shown in Equation (10).
Step 2: calculate the quotient q and the remainder r as shown in Equations (11) and (12).
Step 3: add the q numbers of 0 s.
Step 4: add the truncation code 1.
Step 5: add the remainder r.
b = M
q = N / M
r = N % M
where b is required for the remainder, while q and r are quotient and remainder, respectively.
If the M value is smaller, the number of bits in the remainder will decrease but the quotient will increase. Conversely, if it is larger, the number of bits in the remainder will increase but, in the quotient, it will decrease. Here are three different values of M for testing as shown in Table 2. Table 3 is the encoding result of Golomb–Rice coding with M = 4.

3. The Proposed Lossy Image Compression Hardware Design

Real-time processing is the primary goal of the lossy image compression hardware design proposed in this research. The VLSI design for the proposed image compression technique is presented in Figure 6. The RGB to YEF conversion module, RAM, parameter calculator, BTC training, prediction, Golomb–Rice coder, and packer are all included in the hardware design.
The parameter calculator architecture shown in Figure 7 is used to calculate the minimum, maximum, and average values for each block because the BTC algorithm used in this proposal is based on a 4 × 4 block size. In order to calculate the MAE in the BTC training module, there is a need to store the input values in the line buffer and shift them with each clock. The BTC training module generates the two best reconstructions and bitmap of each block. The prediction module determines the difference in pixel values between the actual and predicted values and quantizes it to conserve the number of bits. Finally, the Golomb–Rice coder module and the packer module pack bit streams once they have been encoded. The packer module consists of three-line buffers and a multiplexer. First, it outputs the Bitmap; second, it encodes the reconstruction value a; and finally, it encodes the reconstruction value b.

3.1. BTC and Golomb–Rice Coding

The BTC training is the most important part of this proposal and the overall hardware architecture. This module finds the best reconstruction value and bitmap for each block. Block diagrams for BTC and Golomb–Rice encoding are shown in Figure 8, including all calculations of the training in parallel time, replacing the original periodic training to improve the throughput and achieve real-time hardware design.
According to formulas (7) and (8), the hardware circuit will be implemented in the reconstruction calculator module. Floating-point calculation of parameters can use shifters and adders to reduce the circuit area. In addition, there is also a line buffer to store the previous pixel value. The bitmap generator calculates the MAE and simultaneously generates the threshold-optimized bitmap. This design of a bitmap generator circuit architecture calculates 25 terms of reconstruction values in parallel, which reduces the processing time. Reconstruction values a0 and b0 are used as an example as shown in Figure 9. The circuit of “Compare” finds the smallest MAE value, which can determine the best reconstruction value and Bitmap.

3.2. Prediction

The prediction module is composed of an adder, a subtractor, four registers, and a quantization table as shown in Figure 10. The register “pre” stores the previous reconstruction value, “diff” stores the difference between the current reconstruction value and the previous predicted reconstruction value, “temp” stores the prediction result of the previous reconstruction value, and “re” stores the prediction error after quantization. The quantized result is stored in the “out” register and outputs every 16 clocks.

3.3. Golomb–Rice Coder

The circuit architecture and FSM of the Golomb–Rice coder are illustrated in Figure 11 and Figure 12. The coding parameter M is set to 4 in this study. The concept is to divide the input signal by four and add a one-bit truncation code and two-bit remainder where the lowest two input signal bits will be the output representing the remainder in the Golomb–Rice code.

4. Results

The quality of this approach and other algorithms may be measured and compared using the byte per pixel (BPP), peak signal-to-noise ratio (PSNR), and compression ratio (CR). The compression ratio (CR) is the ratio of the data before compression to the data after compression. The higher the compression ratio, the less pixel redundancy in the image. This is computed using the formula in Equation (13).
C o m p r e s s i o n   R a t i o = T h e   s i z e   o f   i m a g e   b e f o r e   c o m p r e s s i o n T h e   s i z e   o f   i m a g e   a f t e r   c o m p r e s s i o n
In an uncompressed RGB image, any pixel is represented by 8 bits. After image compression, the total number of bits in the entire image is reduced and each pixel can be represented by fewer bits. When the BPP value is smaller, the compression rate is higher. This is another index that can define the compression rate which is represented using Equation (14):
B P P = T o t a l   n u m b e r   o f   b i t s   a f t e r   c o m p r e s s i o n N u m b e r   o f   p i x e l s
The PSNR is the maximum possible signal-to-mean square error ratio (MSE). It becomes harder to discern between original and decompressed distortion for higher PSNR. It is a measure of image quality and follows Equations (15) and (16):
P S N R = 10 M A X 2 M S E
M S E = 1 m n i = 0 m 1 j = 0 n 1 I i , j K i , j 2
MSE is short for mean square error. The original pixel and the decompressed pixel are denoted by I i , j and K i , j , respectively, and MAX denotes the highest pixel value in the m × n size image.
Figure 13 and Figure 14 show the test images used in this study, which are widely used as test images for image compression techniques. Table 4 and Table 5 provide the outcomes for CR, BPP, and PSNR. Table 4 displays the outcomes from utilizing Figure 13, which is the Kodak photo collection [24]. Table 4 presents the results of the analysis using four test images (Figure 13).
Table 6 lists the image compression performance of this study compared with other BTC algorithms. In terms of CR and BPP, the algorithm outperforms the existing 4 × 4 BTC methods [25]. FOM is defined as an index of compression performance to objectively judge image quality. The concept combines the performance of compression rate and PSNR as shown in Formula (17).
F O M = C R × P S N R
The designed chip performs very well in terms of throughput. It can compress up to 50 frames per second for full-high-definition (FHD) images. Table 7 lists the chip information simulated using the EDA tool.
This study employs a pipelined chip architecture to achieve high-throughput compression operations. In addition, it also computes three-color planes in parallel. The revised hardware architecture is shown in Figure 15.

5. Conclusions

Image transmission has become a significant burden because of the increasing volume of data. Compression techniques must be used to achieve faster data transmission while maintaining image quality. This research proposes a low-complexity, high-compression-ratio image compression method and develops a real-time color image compression VLSI design. Color sampling technology is employed in the new BTC algorithm to reduce computing complexity and enhance compression ratio. The experimental findings demonstrate that utilizing machine learning to train several BTC parameters in order to acquire the best parameter solution yields good results. According to the comparison results, the suggested technique has the best compression performance and the highest throughput. The FOM was successfully improved by 33% as a result. In addition, the BTC algorithm now includes a threshold optimization mechanism to prevent image distortion. To lessen the cost of sampling redundant data and to address the difficult issue of enormous data transfer in the Internet of Things, using cutting-edge technologies can be expected for further improvements in the future. The readout circuit can boost the frame rate of high-speed image sensors or reduce power consumption. Large-scale image sensors will be demonstrated in the future, along with the improvement of effective sampling algorithms and further noise and power consumption reductions.

Author Contributions

Conceptualization, H.-S.C. and S.-Y.K.; data curation, H.-S.C. and S.-Y.K.; formal analysis, M.-L.C. and T.-Y.C.; funding acquisition, S.-L.C. and C.-A.C.; methodology, S.-L.C., H.-S.C. and S.-Y.K.; resources, C.-A.C. and L.-H.W.; software, S.-L.C., H.-S.C. and S.-Y.K.; supervision, C.-A.C. and S.-L.C.; validation, K.-C.L.; visualization, H.-S.C., P.A.R.A. and K.-C.L.; writing—original draft, H.-S.C. and S.-Y.K.; writing—review & editing, M.-L.C., T.-Y.C. and P.A.R.A. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the Ministry of Science and Technology (MOST), Taiwan, under grant numbers MOST 111-2221-E-033-041, MOST 111-2823-8-033-001, MOST 110-2223-8-033-002, MOST 110-2221-E-027-044-MY3, MOST 110-2218-E-035-007, MOST 110-2622-E-131-002, MOST 109-2622-E-131-001-CC3, and the National Chip Implementation Center, Taiwan.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The authors declare no conflict of interest.

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  26. Lian, C.J.; Chen, L.G.; Chang, H.C.; Chang, Y.C. Design and implementation of JPEG encoder IP core. In Proceedings of the 2001 Asia and South Pacific Design Automation Conference, Yokohama, Japan, 30 January–2 February 2001; pp. 29–30. [Google Scholar] [CrossRef]
  27. Olyaei, A.; Genov, R. CMOS wavelet compression imager architecture. In Proceedings of the 2005 IEEE 7th CAS Symposium on Emerging Technologies: Circuits and Systems for 4G Mobile Wireless Communications, St. Petersburg, Russia, 23–24 June 2005; pp. 104–107. [Google Scholar] [CrossRef]
Figure 1. The image compression algorithm flowchart enhanced from BTC proposed in this research.
Figure 1. The image compression algorithm flowchart enhanced from BTC proposed in this research.
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Figure 2. The distribution of color intensities in R, G, and B.
Figure 2. The distribution of color intensities in R, G, and B.
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Figure 3. Equivalent distribution of pixels in YEF color space.
Figure 3. Equivalent distribution of pixels in YEF color space.
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Figure 4. Four types of 4:2:0 sampling format.
Figure 4. Four types of 4:2:0 sampling format.
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Figure 5. The 4:2:2 sampling of the reconstruction value and bitmap.
Figure 5. The 4:2:2 sampling of the reconstruction value and bitmap.
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Figure 6. Block diagram of the proposed hardware architecture.
Figure 6. Block diagram of the proposed hardware architecture.
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Figure 7. The modular structure of this study. (a) Register bank module. (b) Parameter calculator module.
Figure 7. The modular structure of this study. (a) Register bank module. (b) Parameter calculator module.
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Figure 8. The block diagram of BTC and Golomb–Rice coding.
Figure 8. The block diagram of BTC and Golomb–Rice coding.
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Figure 9. The architecture of the BTC training module. State 1 is calculating the different between current value, a0, and b0. State 2 is comparing the different from State 1. State 3 is calculating the MAE value and deciding the best reconstruction value and bitmap.
Figure 9. The architecture of the BTC training module. State 1 is calculating the different between current value, a0, and b0. State 2 is comparing the different from State 1. State 3 is calculating the MAE value and deciding the best reconstruction value and bitmap.
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Figure 10. The architecture of the prediction module.
Figure 10. The architecture of the prediction module.
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Figure 11. FSM of Golomb–Rice coder module.
Figure 11. FSM of Golomb–Rice coder module.
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Figure 12. The architecture of the Golomb–Rice coder module. State 1 to State 3 are calculating the quantization value and coding. State 4 to 6 are controlling the output value about encoder.
Figure 12. The architecture of the Golomb–Rice coder module. State 1 to State 3 are calculating the quantization value and coding. State 4 to 6 are controlling the output value about encoder.
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Figure 13. Kodak 24 images [24].
Figure 13. Kodak 24 images [24].
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Figure 14. Four test images.
Figure 14. Four test images.
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Figure 15. Block diagram of the revised hardware architecture. State 1 is converting RGB color space to YEF color space. State 2 is calculating the max and min of Y. State 3 is calculating the value of reconstruction value and bitmap. State 4 is calculating the MAE which is helpful to decide the best reconstruction value. State 5 is quantizing the reconstruction value. State 6 is coding the reconstruction value with Golomb-rice.
Figure 15. Block diagram of the revised hardware architecture. State 1 is converting RGB color space to YEF color space. State 2 is calculating the max and min of Y. State 3 is calculating the value of reconstruction value and bitmap. State 4 is calculating the MAE which is helpful to decide the best reconstruction value. State 5 is quantizing the reconstruction value. State 6 is coding the reconstruction value with Golomb-rice.
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Table 1. Quantization table for the encoder and decoder.
Table 1. Quantization table for the encoder and decoder.
Encoder (Quantizer)Decoder
RangeOutputRangeOutputEncoder CodeOutputEncoder CodeOutput
−1~102~410013
−4~−225~732−336
−7~−548~1054−659
−10~−18611~1576−9713
−15~−11816~2098−13918
−20~−161021~271110−181124
−27~−211228~341312−241331
−34~−281435~411514−311538
−41~−351642~501716−381746
−50~−421851~591918−461955
−59~−512060~702120−552165
−70~−602271~812322−652376
−82~−712482~942524−762588
−94~−832695~1072726−8827101
−107~−9528108~1202928−10129114
≤−10830≥1213130−11431127
Table 2. Comparison of compression ratio in different M values.
Table 2. Comparison of compression ratio in different M values.
M ValueM = 8M = 4M = 2
Lenna13.204913.192912.5449
Airplane12.106612.662212.3934
Peppers12.704712.953112.4891
Baboon12.728612.979812.497
Average12.686212.94712.4811
Table 3. Golomb–Rice coding table used in this research.
Table 3. Golomb–Rice coding table used in this research.
Difference RangeRegionQuotientRemainderCodewordLength
−1~10001003
2~41011013
−4~−22021103
5~73031113
−7~−541001004
8~1051101014
−10~−861201104
11~1571301114
−15~−11820001005
16~20921001015
−20~−161022001105
21~271123001115
−27~−2112300001006
28~3413310001016
−34~−2814320001106
35~4115330001116
−41~−35164000001007
42~50174100001017
−50~−42184200001107
51~59194300001117
−59~−512050000001008
60~702151000001018
−70~−602252000001108
71~812353000001118
−81~−7124600000001009
82~9425610000001019
−94~−8226620000001109
95~10727630000001119
−107~−952870000000010010
108~1202971000000010110
≤−1083072000000011010
≥1213173000000011110
Table 4. Resulting CR, PSNR, and BPP using the test images in Figure 14.
Table 4. Resulting CR, PSNR, and BPP using the test images in Figure 14.
CRPSNRBPP
Kodak_112.922126.52090.6191
Kodak_213.541229.55400.5908
Kodak_313.513330.64020.5920
Kodak_413.379529.71390.5979
Kodak_512.563825.35760.6368
Kodak_613.359228.38880.5988
Kodak_713.232029.45350.6046
Kodak_812.417324.48780.6443
Kodak_913.398329.76490.5971
Kodak_1013.342830.39100.5996
Kodak_1113.273428.85710.6027
Kodak_1213.554330.37690.5902
Kodak_1312.769024.98740.6265
Kodak_1413.019326.67300.6145
Kodak_1513.295428.75670.6017
Kodak_1613.579031.36370.5891
Kodak_1713.160330.42850.6079
Kodak_1812.983227.37330.6162
Kodak_1913.207828.26180.6057
Kodak_2013.512829.24680.5920
Kodak_2113.313828.33920.6009
Kodak_2213.242129.19590.6041
Table 5. Resulting in CR, PSNR, and BPP using the test images in Figure 14.
Table 5. Resulting in CR, PSNR, and BPP using the test images in Figure 14.
CRPSNRBPP
Lenna12.953127.99870.6176
Airplane13.192926.87230.6064
Peppers12.979825.27050.6163
Baboon12.662222.37270.6318
Average12.94725.62860.618
Table 6. Results with other BTC algorithms and this work.
Table 6. Results with other BTC algorithms and this work.
PSNR/BPP
This Work4 × 4 BTC [25]AMBTC [20]
Average PSNR26.71/0.6231.02/1.1230.49/1.00
Average CR12.9037.14288
FOM334.6391221.5696243.92
Table 7. Chip specification of this work and other chip designs.
Table 7. Chip specification of this work and other chip designs.
This Work4 × 4 BTC [25]JPEG [26]2D Haar [27]
CompressionBTC + Golomb–Rice CodingBTC +Golomb–Rice CodingJPEG2D Haar
TechnologyTSMC 0.18- μ mTSMC 0.18- μ mTSMC 0.6- μ m0.35- μ m
Frequency (MHz)10010040100
Power (mW)45.462.91310N/A
Gate counts (k)56.48.153.4N/A
Core area (k)598.888128,783N/A
Throughput (MPixels)30010040100
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Chen, S.-L.; Chou, H.-S.; Ke, S.-Y.; Chen, C.-A.; Chen, T.-Y.; Chan, M.-L.; Abu, P.A.R.; Wang, L.-H.; Li, K.-C. VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT. Sensors 2023, 23, 1573. https://doi.org/10.3390/s23031573

AMA Style

Chen S-L, Chou H-S, Ke S-Y, Chen C-A, Chen T-Y, Chan M-L, Abu PAR, Wang L-H, Li K-C. VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT. Sensors. 2023; 23(3):1573. https://doi.org/10.3390/s23031573

Chicago/Turabian Style

Chen, Shih-Lun, He-Sheng Chou, Shih-Yao Ke, Chiung-An Chen, Tsung-Yi Chen, Mei-Ling Chan, Patricia Angela R. Abu, Liang-Hung Wang, and Kuo-Chen Li. 2023. "VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT" Sensors 23, no. 3: 1573. https://doi.org/10.3390/s23031573

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