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Communication

Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs)

1
Department of Electrical Engineering, Pohang University of Science and Technology (POSTECH), Pohang 37673, Republic of Korea
2
Department of Electrical Engineering, Gyeongsang National University, Jinju 52828, Republic of Korea
*
Author to whom correspondence should be addressed.
Micromachines 2024, 15(4), 481; https://doi.org/10.3390/mi15040481
Submission received: 18 February 2024 / Revised: 26 March 2024 / Accepted: 29 March 2024 / Published: 30 March 2024
(This article belongs to the Section D1: Semiconductor Devices)

Abstract

:
In this study, we investigated the influence of quasi-one-dimensional (Quasi-1D) characteristics on the source and drain contact resistances within vertical nanowire (NW) field-effect transistors (FETs) of diminutive diameter. The top contact of the NW is segregated into two distinct regions: the first encompassing the upper surface, designated as the axial contact, and the second encircling the side surface, known as the radial contact, which is formed during the top-contact metal deposition process. Quantum confinement effects, prominent within Quasi-1D NWs, exert significant constraints on radial transport, consequently inducing a noticeable impact on contact resistance. Notably, in the radial direction, electron tunneling occurs only through quantized, discrete energy levels. Conversely, along the axial direction, electron tunneling freely traverses continuous energy levels. In a meticulous numerical analysis, these disparities in transport mechanisms unveiled that NWs with diameters below 30 nm exhibit a markedly higher radial contact resistance compared to their axial counterparts. Furthermore, an increase in the overlap length (less than 5 nm) contributes to a modest reduction in radial resistance; however, it remains consistently higher than the axial contact resistance.

1. Introduction

The relentless miniaturization of transistors has driven the relentless pursuit of advancements to mitigate short-channel effects (SCEs) and bolster transistor performance. Strain engineering, high-κ/metal gate (HKMG) materials, and three-dimensional fin field-effect transistors (FinFETs) represent some of the key breakthroughs in this ongoing quest [1,2,3]. FinFETs, leveraging SiGe channels and extreme ultraviolet (EUV) lithography, have successfully achieved scaling down to the 5 nm regime. Gate-all-around (GAA) structures, encompassing nanowires and nanosheets, are actively being explored for technology nodes beyond 5 nm due to their superior gate controllability and enhanced current drivability characteristics [4,5,6]. Among these innovations, vertical nanowire FETs (VNWFETs) have emerged as a frontrunner for sub-3 nm technology nodes, owing to their inherent advantages in design flexibility and their ability to achieve high-density integration facilitated by the vertical channel fabrication process [7,8].
However, despite the aforementioned advantages, VNWFETs face unique challenges in contact formation.
Unlike conventional transistors, the vertical fabrication process necessitates the creation of separate contacts on both the bottom and top sides of the device. While the bottom contact analysis can use established methods, the top contact demands a more nuanced approach due to its geometrical complexity. It comprises two distinct interfaces: the circular top surface (axial contact) and the surrounding side surface (radial contact), formed during top-contact metal deposition. Addressing these contact formation challenges is paramount to propel VNWFET technology towards practical applications in next-generation electronic devices.
As the width of the nanowire (NW) shrinks, its characteristics transition towards a quasi-one-dimensional (Quasi-1D) regime. Consequently, investigating contact resistance with due consideration for NW dimensions becomes increasingly important [9,10,11,12]. Prior studies employed compact modeling to analyze parasitic components within structurally asymmetric VNWFETs, specifically focusing on 10–15 nm nanowires [13]. This modeling approach, which utilized a constant contact resistivity parameter, revealed that the top and bottom electrode asymmetry leads to imbalances in parasitic resistance and capacitance, ultimately impacting device performance. However, as NW dimensions approach the sub-10 nm scale, quantum confinement effects come into play. These effects, including bandgap widening and subband splitting, cause the nanowire’s characteristics to deviate significantly from bulk properties, profoundly influencing the contact characteristics at the metal–semiconductor interface [14].
In this study, we used a semi-classical approach that incorporates one-dimensional (1D) quantum effects specific to the top contact structure of VNWFETs. As NW dimensions decrease, the relevant density of states (DOS) exhibits a transition towards Quasi-1D characteristics, distinct from bulk behavior. This phenomenon has a significant impact on the tunneling mechanisms in both the axial and radial directions. By accounting for these quantum confinement effects, we investigated the top contact resistance along both the axial and radial directions. Additionally, we analyzed the influence of overlap distance on the contact resistance. This comprehensive examination aims to shed light on the intricate behavior of VNWFETs, a crucial step towards their continued development and practical implementation in nanoelectronic devices.

2. Modeling of Q1D Transport in Top Contact

Figure 1 shows a schematic diagram of a vertical nanowire (NW) structure where the top contact comprises two interfaces: one covering the top surface, referred to as the axial contact, and the other covering the side surface with an overlap length Lov, referred to as the radial contact.
To take into account the quantum confinement effect of the Si nanowire, the quantized energy states of the NWs can be calculated by solving the Schrödinger equation to determine the discrete energy levels, as expressed by [15]:
E c , n = 2 π 2 n 2 m * W N W 2 ,
where ℏ denotes the reduced Planck constant, n represents the quantum number for the confined direction, m* is the effective mass of the electron, and WNW represents the width of the square NW. This equation provides insight into the behavior of electrons within the nanowire, crucial for understanding VNWFET characteristics and optimizing device performance for advanced electronic applications.
Figure 2 depicts the relationship between the width of the nanowire (WNW) and the number of effective subbands it possesses. These subbands are defined as the quantized energy levels within a specific range, encompassing the lowest subband energy (Ec,0) and extending up to Ec,0 + 4kT. The inset of Figure 2 provides a more detailed illustration of these quantized energy levels, calculated using Equation (1) as a function of WNW. At room temperature, the Fermi–Dirac probability function (f(E)) indicates that approximately 98% of the electrons populate the subbands that fall within the 4kT energy range. Notably, a crucial observation from Figure 2 is the significant decrease in the number of effective subbands that significantly influence electron transport. This number rapidly diminishes to 10 or fewer subbands when the WNW falls below 10 nm.
Continuing our analysis with reference to the energy band diagram presented in Figure 3, we can examine the mechanism of electron transport within the nanowire for both the axial and radial contacts. In both cases, electron transport occurs through a process known as field-emission tunneling. Under the assumption that the source/drain (S/D) extension regions are sufficiently doped, the metal–nanowire interface is typically modeled as an Ohmic-like Schottky contact. This assumption is based on the nanowire possessing a sufficiently small width and a doping concentration of 1 × 1020 cm−3. However, a critical distinction between the axial and radial contacts arises due to the influence of a parameter stemming from the inherent Quasi-1D quantum effects.
The density of states (DOS) in the axial direction of the nanowire of each subband energy can be calculated using the following equation [12]:
g E = 1 π m * 2 E E c , n ,
where E is the energy of the electron, and Ec,n are the quantized subband levels. In an NW with a sub-nanometer diameter and significant length, carrier motion is confined to a 1D space. Consequently, carriers traverse a continuous spectrum of energy states along the wire’s axis, while their motion in the radial direction is constrained to specific quantized energy levels. In the axial contact, tunneled electrons encounter a continuum of energy levels, whereas along the radial direction, they encounter discrete energy levels. The tunneling probability was calculated using the Wentzel–Kramers–Brillouin (WKB) approximation method, which is expressed as
T E = e x p 8 3 ϵ s m * q N d ϕ B V ,
where ϵs is the permittivity of the semiconductor, Nd is the doping concentration of the semiconductor, ϕB is the tunneling barrier height, and V is the bias voltage.
The tunneling thickness was determined by calculating the depletion width of the metal–semiconductor contact using the formula W d = ( ( 2 ϵ s ( ϕ B V ) ) / ( q N d ) ) , where Fermi-level pinning effects were disregarded due to the specific charge characteristics of one-dimensional nanowires [16]. The tunneling barrier height (ϕB) for both the axial and radial contacts was obtained using Equations (4) and (5), respectively. As shown in Figure 3, electrons encounter distinct barrier heights depending on their transport directions. Those tunneling through the axial direction face a continuum of energy states, suggesting that the axial barrier height is continuous, given by
ϕ B , a x = ϕ M S E E c , 0
Those traversing the radial direction face the quantized barrier heights that depend on the quantized levels:
ϕ B n , r a d = ϕ M S E c , n
For the metal contacts, titanium was selected, commonly employed as the initial layer in modern CMOS processes, setting the metal–semiconductor work function difference ( ϕ M S ) to 0.3 eV in this scenario.

3. Calculation of Axial and Radial Contact Resistances

Figure 4a shows the contact resistance of the axial (Rax) and radial (Rrad) contacts, determined from the current density calculated using the following equation:
J S M = q v E c , 0 E c , 0 + 4 k T g E f E T E d E ,
where q is the electron charge, v is the velocity of the electron, k is the Boltzmann constant, T is the temperature, g(E) is the density of states, f(E) is the Fermi–Dirac distribution probability, and T(E) is the tunneling probability.
In the case of a 30 nm nanowire width (WNW), our proposed approach yields results for the axial contact resistance (Rax) and radial contact resistance (Rrad) that are comparable to those obtained using the previously established constant contact resistivity (ρc) model, which uses experimentally determined contact resistivity values [13]. This suggests that for larger-diameter NWs, the ρc model can provide a reasonable approximation. However, the ρc model suggests that the radial resistance (Rrad) can be lowered compared to the axial resistance (Rax) by simply adjusting the overlap length (Lov). For instance, with an overlap length of 5 nm and WNW of 10 nm, the ρc model predicts an axial resistance of approximately 20 Ω and a radial resistance of approximately 10 Ω. This implies that the total contact resistance can be primarily attributed to the combined effects of both axial and radial resistances. However, for NW diameters below 15 nm, a significant discrepancy emerges between the two models. As previously mentioned, only quantized energy levels are relevant for electron transport in the radial direction. Consequently, the influence of WNW on radial resistance becomes considerably more pronounced compared to in the axial direction, highlighting the limitations of the ρc model for sub-15 nm NWs. Consequently, even with an augmented Lov, Rrad consistently maintains higher values than Rax.
In Figure 4b, the influence of Rax and Rrad on the total resistance of the top contact, Rtot, is shown. According to our proposed model, due to the quantum confinement effect, Rrad consistently exhibits a larger value compared to Rax regardless of Lov. Therefore, Rtot can be represented as the parallel of Rax and Rrad, confirming that it is primarily determined by Rax.

4. Conclusions

This investigation explores the impact of contact structure on the electrical characteristics of quasi-one-dimensional vertical nanowire field-effect transistors (VNWFETs). These devices feature a distinctive top contact, consisting of two regions: the upper circular area and the circumferential contact encircling the sidewall. Due to the inherent one-dimensional nature of these contact interfaces, they exhibit distinct contact resistance behaviors. The conventional method of calculating contact resistance, based on contact area and specific contact resistivity between the metal and semiconductor, proves inadequate for nanowire contacts with sub-nanometer diameters due to quantum confinement effects. In Quasi-1D VNWFETs, electrons traveling in the radially confined direction encounter strictly quantized energy levels, greatly limiting their tunneling probability compared to the continuous energy states available along the axial direction. Consequently, as nanowire dimensions decrease, electron tunneling in the radial direction experiences a significant reduction in current compared to tunneling along the axial direction. This critical observation underscores the necessity of considering both distinct interface types for effective device performance optimization. Our findings emphasize the crucial need for accurate modeling of quantum confinement effects, particularly in VNWFETs approaching or falling below the 10 nm threshold.

Author Contributions

Conceptualization, I.P.; investigation, I.P. and J.C.; methodology, I.P., J.K. and B.D.K.; data curation, I.P. and J.-S.L.; writing—original draft preparation, I.P. and J.-S.L.; writing—review and editing, I.P., J.-S.L. and B.D.K.; supervision, J.-S.L. and B.D.K. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported by the National R&D Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (2020M3H2A1078045).

Data Availability Statement

The data presented in this study are available on request from the corresponding author. The data are not publicly available due to confidentiality request.

Conflicts of Interest

The authors declare no conflicts of interest.

References

  1. Chidambaram, P.R.; Bowen, C.; Chakravarthi, S.; Machala, C.; Wise, R. Fundamentals of silicon material properties for successful exploitation of strain engineering in modern CMOS manufacturing. IEEE Trans. Electron Devices 2006, 53, 944–963. [Google Scholar] [CrossRef]
  2. Wu, C.C.; Lin, D.W.; Keshavarzi, A.; Huang, C.H.; Chan, C.T.; Tseng, C.H.; Chen, C.L.; Hsieh, C.Y.; Wong, K.Y.; Cheng, M.L.; et al. High performance 22/20nm FinFET CMOS devices with advanced high-k/metal gate scheme. In Proceedings of the 2010 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 6–8 December 2010. [Google Scholar]
  3. Tang, S.H.; Chang, L.; Lindert, N.; Choi, Y.-K.; Lee, W.-C.; Huang, X.; Subramanian, V.; Bokor, J.; King, T.-J.; Hu, C. FinFET-a quasiplanar double-gate MOSFET. In Proceedings of the 2001 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 7 February 2001. [Google Scholar]
  4. Bangsaruntip, S.; Cohen, G.M.; Majumdar, A.; Zhang, Y.; Engelmann, S.U.; Fuller, N.C.M.; Gignac, L.M.; Mittal, S.; Newbury, J.S.; Guillorn, M.; et al. High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. In Proceedings of the 2009 IEEE International Electron Devices Meeting (IEDM), Baltimore, MD, USA, 7–9 December 2009. [Google Scholar]
  5. Lauer, I.; Loubet, N.; Kim, S.D.; Ott, J.A.; Mignot, S.; Venigalla, R.; Yamashita, T.; Standaert, T.; Faltermeier, J.; Basker, V.; et al. Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance. In Proceedings of the 2015 Symposium on VLSI Technology, Kyoto, Japan, 16–18 June 2015. [Google Scholar]
  6. Mertens, H.; Ritzenthaler, R.; Chasin, A.; Schram, T.; Kunnen, E.; Hikavyy, A.; Ragnarsson, L.-Å.; Dekkers, H.; Hopf, T.; Wostyn, K.; et al. Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates. In Proceedings of the 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 3–7 December 2016. [Google Scholar]
  7. Guerfi, Y.; Larrieu, G. Vertical silicon nanowire field effect transistors with nanoscale gate-all-around. Nanoscale Res. Lett. 2016, 11, 210. [Google Scholar] [CrossRef]
  8. Veloso, A.; Altamirano-Sánchez, E.; Brus, S.; Chan, B.T.; Cupak, M.; Dehan, M.; Delvaux, C.; Devriendt, K.; Eneman, G.; Ercken, M.; et al. Vertical nanowire FET integration and device aspects. ECS Trans. 2016, 72, 31–42. [Google Scholar] [CrossRef]
  9. Shafizade, D.; Shalcian, M.; Jazaeri, F. Ultrathin junctionless nanowire FET model, including 2-D quantum confinements. IEEE Trans. Electron Devices 2019, 66, 4101–4106. [Google Scholar] [CrossRef]
  10. Svensson, J.; Campbell, E. Schottky barriers in carbon nanotube-metal contacts. J. Appl. Phys. 2011, 110, 111101. [Google Scholar] [CrossRef]
  11. Wang, Z.-R.; Zhang, G.; Pey, K.-L.; Tung, C.H.; Lo, P.G.-Q. Schottky-Ohmic transition in metal-all-around electrical nanotubes to silicon nanowires. J. Appl. Phys. 2009, 105, 094508. [Google Scholar] [CrossRef]
  12. Léonard, F.; Talin, A.A. Size-dependent effects on electrical contacts to nanotubes and nanowires. Phys. Rev. Lett. 2006, 97, 026804. [Google Scholar] [CrossRef]
  13. Maheshwaram, S.; Manhas, S.K.; Kaushal, G.; Anand, B.; Singh, N. Vertical nanowire CMOS parasitic modeling and its performance analysis. IEEE Trans. Electron Devices 2013, 60, 2943–2950. [Google Scholar] [CrossRef]
  14. Ma, D.D.D.; Lee, C.S.; Au, F.C.K. Small-diameter silicon nanowire surfaces. Science 2003, 299, 1874–1877. [Google Scholar] [CrossRef] [PubMed]
  15. Yoffe, A.D. Low-dimensional systems: Quantum size effects and electronic properties of semiconductor microcrystallites (zero-dimensional systems) and some quasi-two-dimensional systems. Adv. Phys. 1993, 42, 173–262. [Google Scholar] [CrossRef]
  16. Léonard, F.; Tersoff, J. Role of Fermi-level pinning in nanotube Schottky diodes. Phys. Rev. Lett. 2000, 84, 4693. [Google Scholar] [CrossRef] [PubMed]
Figure 1. A bird’s eye view of a schematic diagram depicting a VNWFET and an enlarged view of the top contact structure of the VNWFET.
Figure 1. A bird’s eye view of a schematic diagram depicting a VNWFET and an enlarged view of the top contact structure of the VNWFET.
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Figure 2. The number of effective subbands in the 4kT energy box from the lowest subband energy. Inset: the calculated subband energy with various widths of nanowire in the 5~30 nm range.
Figure 2. The number of effective subbands in the 4kT energy box from the lowest subband energy. Inset: the calculated subband energy with various widths of nanowire in the 5~30 nm range.
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Figure 3. Schematic diagrams of an energy band in (a) the axial direction and (b) the radial direction with the corresponding DOS in a Quasi-1D metal–NW contact.
Figure 3. Schematic diagrams of an energy band in (a) the axial direction and (b) the radial direction with the corresponding DOS in a Quasi-1D metal–NW contact.
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Figure 4. (a) Calculated contact resistance of axial (Rax) and radial (Rrad) contacts with varying WNW and Lov. The asterisks (*) denote values calculated using the constant ρc model [13] and (b) Rax (solid), Rrad (dot), and Rtot (=Rax∥Rrad) (dash) with varying WNW and overlap lengths (Lov = 1, 3, and 5 nm).
Figure 4. (a) Calculated contact resistance of axial (Rax) and radial (Rrad) contacts with varying WNW and Lov. The asterisks (*) denote values calculated using the constant ρc model [13] and (b) Rax (solid), Rrad (dot), and Rtot (=Rax∥Rrad) (dash) with varying WNW and overlap lengths (Lov = 1, 3, and 5 nm).
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MDPI and ACS Style

Park, I.; Choi, J.; Kim, J.; Kong, B.D.; Lee, J.-S. Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs). Micromachines 2024, 15, 481. https://doi.org/10.3390/mi15040481

AMA Style

Park I, Choi J, Kim J, Kong BD, Lee J-S. Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs). Micromachines. 2024; 15(4):481. https://doi.org/10.3390/mi15040481

Chicago/Turabian Style

Park, Iksoo, Jaeyong Choi, Jungsik Kim, Byoung Don Kong, and Jeong-Soo Lee. 2024. "Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs)" Micromachines 15, no. 4: 481. https://doi.org/10.3390/mi15040481

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