A Review of Research on Traffic Modeling for NoC

DOI

10.2991/iceeecs-16.2016.124How to use a DOI?

Keywords

Network-on-Chip; Traffic modeling; Application specific

Abstract

NoC (Network on Chip), as a promising interconnection infrastructure for MPSoC (Multi-Processor System-on-Chip), has been the research focus since its invention. Accurate traffic models are necessary to deplore the vast design space of NoC. In this paper, we survey the researching works on the traffic modeling of NoC by referring and comparing to the development pattern of the traffic models in packet-switched computer networks, and try to figure out the direction of the next step.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Haiyun Gu
AU  - Hua Bo
AU  - Lei Ren
PY  - 2016/12
DA  - 2016/12
TI  - A Review of Research on Traffic Modeling for NoC
BT  - Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SP  - 623
EP  - 627
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.124
DO  - 10.2991/iceeecs-16.2016.124
ID  - Gu2016/12
ER  -