Indian Journal of Science and Technology
DOI: 10.17485/ijst/2016/v9iS1/105939
Year: 2016, Volume: 9, Issue: Special Issue 1, Pages: 1-7
Original Article
Neetu Goel1 , Neeraj Kr. Shukla2 and Shilpi Birla3
1,2VLSI Group, Department of EECE, The Northcap University, Gurgaon 122017, Haryana, India; [email protected]
[email protected]
3 ECE Department, Manipal University, Jaipur 303007, Rajasthan, India
Objectives: Implementation of Verification IP with randomized stimulus and coverage for Avalon Memory Mapped interface using Universal Verification Methodology (UVM). Methods/Statistical Analysis: The VIP is implemented using UVM. The unique feature of UVM is its reusability. All the UVM components are implemented to create the VIP for AValon Memory Mapped (AVMM) interface. The environment uses random stimuli to create different scenarios and improves coverage during regression. The coverage collection measures how much verification goal is achieved. Findings: The VIP created is unique and novel as it is flexible and scalable and allows user to modify according to the need. The factory pattern and phased test flow makes it versatile and reusable to plug and play in any SOC. The cover groups and coverage bins gives the report on what features has been covered and what needs to be exercised. The functional coverage achieved with implemented VIP is 91.6% Application/Improvements: AVMM interface is used to provide communicate between various components. The AVMM VIP can be used for verification in any SOC that uses AVMM interface. The random environment can be constrained to fill the coverage holes.
Keywords: Functional Coverage, Regression, SOC, Universal Verification Methodology, Verification IP
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