Öz
Hardware security gained more attention due to the widespread use of cloud computing and remote execution, where multiple executions share a computer's resources. It is possible to extract confidential information such as cryptographic keys through cache-based side-channel attacks as in Meltdown and Spectre attacks, and as a result, secure cache architectures have become one of the hot research topics in the computer architecture field, today. These architectures come with an inevitable performance penalty since there is always an overhead for hiding information from the attackers. Subsequently, the performance degradation is traded off with the improvement in security. In this thesis, we analyze cache-based side-channel attacks, and the performance deterioration of the existing architectures and come up with a new solution which improves the fairness of the general framework.
We propose a secure cache mechanism that respects fairness among the competing threads within a processor. We evaluate our proposed architecture in 4-threaded and 8-threaded processors. As a result, we obtain 38.6% performance gain over SecDCP (Secure and Dynamic Cache Partitioning) on the average, in a 4-threaded system. We show that we can achieve up to 8.7% performance improvement over the baseline, 9.2% better performance compared to the static partitioning and 14.1% performance gain over SecDCP on the average, in an 8-threaded system. We also achieve almost identical results in terms of the fairness metric compared to a non-secure dynamic cache partitioning scheme.
Anahtar Kelimeler
secure caches computer architecture cache-based side-channel attacks
Kaynakça
- C. Rebeiro, D. Mukhopadhyay, and S. Bhattacharya,Timing channels in cryptography: a micro-architectural perspective. Springer, 2014.
- T. S. Messerges, E. A. Dabbish, and R. H. Sloan, “Investigations of power analysis attacks on smartcards.” Smartcard, vol. 99, pp. 151–161, 1999.
- D. Zhang, Y. Wang, G. E. Suh, and A. C. Myers, “A hardware design language for timing-sensitive information-flow security,” ACM SIGARCH Computer Architecture News, vol. 43, no. 1, pp. 503–516, 2015.
- Z. Wang and R. B. Lee, “New cache designs for thwarting software cache-based side channel attacks,” ACM SIGARCH Computer Architecture News, vol. 35, no. 2, pp. 494–505, 2007.
- Y. Wang, A. Ferraiuolo, D. Zhang, A. C. Myers, and G. E. Suh, “Secdcp: secure dynamic cache partitioning for efficient timing channel protection,” in Proceedings of the 53rd Annual Design Automation Conference. ACM, 2016, p. 74.
- Z. Wang and R. B. Lee, “Covert and side channels due to processor architecture,” in 2006 22nd Annual Computer Security Applications Conference (ACSAC’06). IEEE, 2006, pp. 473–482.
- M. K. Qureshi, “Ceaser: Mitigating conflict-based cache attacks via encrypted-address and remapping,” in 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018,pp. 775–787.
- Z. Wang and R. B. Lee, “A novel cache architecture with enhanced per-formance and security,” in Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture.IEEE Computer Society, 2008, pp. 83–93.
- M. K. Qureshi and Y. N. Patt, “Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches,” in 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’06). IEEE, 2006, pp. 423–432.
- S. K. Sadasivam, B. W. Thompto, R. Kalla, and W. J. Starke, “IBM Power9 processor architecture,”IEEE Micro, vol. 37, no. 2, pp. 40–51, 2017.
- D. Page, “Theoretical use of cache memory as a cryptanalytic side-channel.” IACR Cryptology ePrint Archive, vol. 2002, no. 169, 2002.
- F. Liu and R. B. Lee, “Random fill cache architecture,” in Proceedings Of the 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2014, pp. 203–215.
- C. Percival, “Cache missing for fun and profit,” 2005.
- D. A. Osvik, A. Shamir, and E. Tromer, “Cache attacks and countermeasures: the case of AES,” in Cryptographers track at the RSA conference. Springer, 2006, pp. 1–20.
- D. Gullasch, E. Bangerter, and S. Krenn, “Cache games–bringing access-based cache attacks on AES to practice,” in 2011 IEEE Symposium on Security and Privacy. IEEE, 2011, pp. 490–505.
- Y. Yarom and K. Falkner, “Flush+ reload: a high resolution, low noise,l3 cache side-channel attack,” in 23rd USENIX Security Symposium, 2014, pp. 719–732.
- L. Domnitser, A. Jaleel, J. Loew, N. Abu-Ghazaleh, and D. Ponomarev,“Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 8, no. 4, p. 35, 2012.
- J. Sharkey, D. Ponomarev, and K. Ghose, “M-sim: a flexible, multithreaded architectural simulation environment,”Technical report,Department of Computer Science, State University of New York at Binghamton, 2005.
- K. Luo, J. Gummaraju, and M. Franklin, “Balancing throughput and fairness in SMT processors,” in 2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. IEEE, 2001,pp. 164–171.
Öz
Bulut bilişimin yaygın kullanımı, sanallaştırma ve uzaktan çalıştırma nedeniyle sunucu kaynaklarının birden fazla bilgisayar tarafından paylaşılması, donanımı paylaşılan bir kaynak haline getirmiş,ve donanım güvenliği daha fazla önem kazanmaya başlamıştır. Meltdown ve Spectre saldırılarında olduğu gibi önbellek tabanlı yan kanal saldırıları yoluyla şifreleme anahtarları gibi gizli bilgileri çıkarmak mümkündür. Güvenli donanım çalışmaları içinde, güvenli önbellek mimarileri üzerine yapılan çalışmalar daha derin bir odak noktası haline geldi. Güvenli önbellek mimarileri kaçınılmaz bir performans kaybıyla birlikte gelir, çünkü her zaman saldırganlardan bilgi gizlemenin bir işleme ya da saklama maliyeti vardır. Performansın düşüşünü kullanıcılar arasında adil bir şekilde paylaştırmak, güvenlik çözümlerinde göz ardı edilmiştir. Bu çalışma ile birlikte, mevcut mimarilerin performans bozulmalarını analiz edip, genel çerçevenin adaletliliğini artıran yeni bir çözüm sunuyoruz. Önbellek tabanlı yan kanal saldırılarına karşı, bir işlemci içindeki rakip iş parçacıkları arasında adalete saygı duyan güvenli bir önbellek mekanizması öneriyoruz. FairSDP mimarisini 4 iş parçacıklı ve 8 iş parçacıklı işlemcilerde değerlendirdik. Sonuç olarak, 4 iş parçacıklı bir sistemde ortalama olarak SecDCP (Güvenli ve Dinamik Önbellek Bölümleme) mimarisine kıyasla yüzde 38,6 performans artışı elde ediyoruz. 8 iş parçacıklı bir sistemde taban çizgisine göre yüzde 8,7'ye kadar performans iyileştirmesi, statik bölümlemeye kıyasla yüzde 9,2 daha iyi performans ve ortalama olarak SecDCP'ye göre yüzde 14,1 performans artışı sağlayabildiğimizi gösteriyoruz. Ayrıca, güvenli olmayan bir dinamik önbellek bölümleme tekniğine kıyasla adalet metriği açısından hemen hemen aynı sonuçları elde ederiz.
Anahtar Kelimeler
güvenli önbellek bilgisayar mimarisi önbellek tabanlı yan kanal saldıraları
Kaynakça
- C. Rebeiro, D. Mukhopadhyay, and S. Bhattacharya,Timing channels in cryptography: a micro-architectural perspective. Springer, 2014.
- T. S. Messerges, E. A. Dabbish, and R. H. Sloan, “Investigations of power analysis attacks on smartcards.” Smartcard, vol. 99, pp. 151–161, 1999.
- D. Zhang, Y. Wang, G. E. Suh, and A. C. Myers, “A hardware design language for timing-sensitive information-flow security,” ACM SIGARCH Computer Architecture News, vol. 43, no. 1, pp. 503–516, 2015.
- Z. Wang and R. B. Lee, “New cache designs for thwarting software cache-based side channel attacks,” ACM SIGARCH Computer Architecture News, vol. 35, no. 2, pp. 494–505, 2007.
- Y. Wang, A. Ferraiuolo, D. Zhang, A. C. Myers, and G. E. Suh, “Secdcp: secure dynamic cache partitioning for efficient timing channel protection,” in Proceedings of the 53rd Annual Design Automation Conference. ACM, 2016, p. 74.
- Z. Wang and R. B. Lee, “Covert and side channels due to processor architecture,” in 2006 22nd Annual Computer Security Applications Conference (ACSAC’06). IEEE, 2006, pp. 473–482.
- M. K. Qureshi, “Ceaser: Mitigating conflict-based cache attacks via encrypted-address and remapping,” in 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2018,pp. 775–787.
- Z. Wang and R. B. Lee, “A novel cache architecture with enhanced per-formance and security,” in Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture.IEEE Computer Society, 2008, pp. 83–93.
- M. K. Qureshi and Y. N. Patt, “Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches,” in 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO’06). IEEE, 2006, pp. 423–432.
- S. K. Sadasivam, B. W. Thompto, R. Kalla, and W. J. Starke, “IBM Power9 processor architecture,”IEEE Micro, vol. 37, no. 2, pp. 40–51, 2017.
- D. Page, “Theoretical use of cache memory as a cryptanalytic side-channel.” IACR Cryptology ePrint Archive, vol. 2002, no. 169, 2002.
- F. Liu and R. B. Lee, “Random fill cache architecture,” in Proceedings Of the 47th Annual IEEE/ACM International Symposium on Microarchitecture. IEEE Computer Society, 2014, pp. 203–215.
- C. Percival, “Cache missing for fun and profit,” 2005.
- D. A. Osvik, A. Shamir, and E. Tromer, “Cache attacks and countermeasures: the case of AES,” in Cryptographers track at the RSA conference. Springer, 2006, pp. 1–20.
- D. Gullasch, E. Bangerter, and S. Krenn, “Cache games–bringing access-based cache attacks on AES to practice,” in 2011 IEEE Symposium on Security and Privacy. IEEE, 2011, pp. 490–505.
- Y. Yarom and K. Falkner, “Flush+ reload: a high resolution, low noise,l3 cache side-channel attack,” in 23rd USENIX Security Symposium, 2014, pp. 719–732.
- L. Domnitser, A. Jaleel, J. Loew, N. Abu-Ghazaleh, and D. Ponomarev,“Non-monopolizable caches: Low-complexity mitigation of cache side channel attacks,” ACM Transactions on Architecture and Code Optimization (TACO), vol. 8, no. 4, p. 35, 2012.
- J. Sharkey, D. Ponomarev, and K. Ghose, “M-sim: a flexible, multithreaded architectural simulation environment,”Technical report,Department of Computer Science, State University of New York at Binghamton, 2005.
- K. Luo, J. Gummaraju, and M. Franklin, “Balancing throughput and fairness in SMT processors,” in 2001 IEEE International Symposium on Performance Analysis of Systems and Software. ISPASS. IEEE, 2001,pp. 164–171.
Ayrıntılar
| Birincil Dil | Türkçe |
|---|---|
| Konular | Mühendislik |
| Bölüm | Makaleler |
| Yazarlar | |
| Yayımlanma Tarihi | 28 Şubat 2022 |
| Gönderilme Tarihi | 30 Mart 2020 |
| Kabul Tarihi | 20 Ağustos 2021 |
| Yayımlandığı Sayı | Yıl 2022 Cilt: 37 Sayı: 2 |