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Three-dimensional integration: An industry perspective

  • Materials challenges in 3D IC technology
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Abstract

The field of electronics packaging is undergoing a significant transition to accommodate the slowing down of lithographically driven semiconductor scaling. Three-dimensional (3D) integration is an important component of this transition and promises to revolutionize the way chips are assembled and interconnected in a subsystem. In this article, we develop the key attributes of 3D integration, the enablers and the challenges that need to be overcome before widespread acceptance by industry. While we are already seeing the proliferation of applications in the memory subsystem, the best is yet to come with the heterogeneous integration of a diverse set of technologies, the mixing of lithographic nodes and an economic argument for its implementation based on overall system function, and cost rather than a narrow component-based analysis. Finally, an extension to monolithic 3D integration promises even further benefits.

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Notes

  1. * A recent retrospective of Dennard’s scaling theory by M. Bohr is available at http://www.eng.auburn.edu/∼agrawvd/COURSE/READING/LOWP/Boh07.pdf and also in the January 2007 issue of the IEEE Journal of Solid-State Circuits Society.

  2. † Latency refers to the time it takes for data to reach its destination after being requested, a measure of delay that includes logic operations and transit time, while bandwidth refers to how much data may be transferred in a unit of time—a measure of how many interconnects exist between two system nodes.

  3. ‡ Hierarchical wiring refers to a progressive increase in both wiring pitch and thickness while moving away from the silicon surface. The levels near the silicon are fine pitch and used for local interconnects. While moving up the hierarchy, one can wire longer distances. Finally, at the uppermost levels, the pitch and thickness are greatest, and these levels are typically used for power bussing, I/O to the chip, and the clock distribution mesh.

  4. § The known good die problem is where one needs to assemble fully tested dies that meet all the specifications of the chip, but some of these specifications may not be verified in die form.

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Acknowledgments

The continued interaction and contributions of all colleagues at IBM, especially Daniel Berger and Gary Patton, are gratefully acknowledged. S.I. would also like to thank Rao Tummala at Georgia Institute of Technology for extensive discussions and insights.

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  1. Microelectronics Division, IBM Systems and Technology Group, USA

    Subramanian S. Iyer

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  1. Subramanian S. Iyer
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Correspondence to Subramanian S. Iyer.

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Iyer, S.S. Three-dimensional integration: An industry perspective. MRS Bulletin 40, 225–232 (2015). https://doi.org/10.1557/mrs.2015.32

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