Abstract:
A binary adder is a primary component of many high-performance architectures like Digital Signal Processing (DSP), Image Processing, and Multimedia Processing. The design of a suitable binary adder in terms of power dissipation, delay, energy efficiency, and silicon chip area is more challenging. To obtain better performance metrics, a new full adder circuit design has been introduced in this paper. Here, three full adder designs are developed based on the Switching Activity (SA) of basic logic gates (AND, OR, and NOT). The SA value of the NOT gate is large compared to the other two logic gates. The proposed full adder is developed based on the logic decomposition method, which reduces the number of NOT gates as well as the overall SA value in the binary adder circuit, which leads to a reduction in dynamic power dissipation and the area of the binary adder circuit. In this paper, three 1-bit Full Adders are designed and their behaviour is described using Verilog HDL, synthesised and implemented in a Xilinx Vivado Zynq-7000 family configurable device. The implementation results indicate that the proposed full adder design yields better performance in comparison with Conventional Full Adder (CFA) and Modified Conventional Full Adder (MCFA) in terms of cell count, delay, power dissipation, and Energy Delay Product (EDP). The proposed full adder is attractive in improving 58.8% in Standard Basic Cell Count (SBCC), 65.9% in dynamic power dissipation and 66% in PDP compared to conventional method and 22.2% in SBCC, 43.8% in dynamic power dissipation and 43.9% in PDP compared to the modified conventional method. Furthermore, a formula-based evaluation is made on performance metrics to get optimal design trade-offs in terms of EDP. The EDP of the proposed full adder is reduced by 66.1% compared to the conventional method and by 44% compared to the modified conventional method.
