Charge Trapping Devices Using a Bilayer Oxide Structure

This experiment is the first exploration of use of charge traps in the bulk of deposited top oxide and at the interface between thermal oxide and deposited top oxide. We report the operational characteristics of SiO₂/SiO₂ device structures with 0.5 μm gate width and length. Low power operations are achieved through very thin gate stacks of 3 nm of thermally grown oxide and 7 nm of deposited oxide. However, narrow memory windows have been acquired comparing with conventional silicon–oxide–nitride–oxide–silicon (SONOS) memory cells due to a low trap density at the interface between a grown oxide and a deposited oxide. Additionally, the electric field between the channel and the charge is determined by solving 1D Poisson equation at a given write voltage, then total tunneling current density is calculated to make a program modeling for charge trapping devices. Tunneling/trapping simulation based on Fowler-Nordheim (F-N) tunneling performed and it fits the programming curves well. The memory window is almost constant after 100,000 cycles, and the retention characteristics are deteriorated rapidly.