Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond

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© 2007 ECS - The Electrochemical Society
, , Citation Dae-Gyu Park et al 2007 ECS Trans. 11 371 DOI 10.1149/1.2778394

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Abstract

This paper provides a forum for reviewing and discussing new elements and challenges in the front end of line (FEOL) process integration for 32nm logic devices in the following areas: Metal/high-k (MHK) gate stack, mobility enhancement substrate technology and strain engineering.

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