Abstract
Strained SiGe channel is attractive to further boost the performance of p-MOS FinFET due to its enhanced intrinsic transport properties and improved reliability compared to Si FinFET. With higher Ge incorporated in the channel, higher mobilities can be achieved, mainly due to the increased level of compressive strain. However, a major challenge is associated with the gate stack and interface trap control as the Ge content is increased. In this paper, key process details to enable relatively tall fins and optimized replacement high-k metal gate (RMG) stacks in high-Ge-content SiGe are discussed and their impact on key device characteristics are presented. In addition, our recent advancements to achieve optimized RMG interface layer and passivation to enable high performance short channel pMOS FinFETs are reviewed.