Abstract
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. Here, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies. Also, planar ultrathin body/ultrathin BOX-based multi-gate structures are preferred to suppress short channel effects and to control Vth in static and/or dynamic way. In this paper, we address several key technologies to enhance the performance of III-V/Ge MOSFETs. In InGaAs/InAs n-channel MOSFETs, a parasitic resistance reduction technique is newly introduced for Ni-InGaAs metal S/D. Sub-20-nm-Lch Tri-gate InGaAs/InAs /InGaAs-OI QW MOSFETs have been demonstrated with good electrostatics. In GaSb p-MOSFETs, a metal S/D technology based on Ni is also applied to GaSb channels. The Ni-GaSb self-aligned S/D GaSb p-MOSFETs have successfully operated. In Ge MOSFETs with GeOx interfacial layers formed by plasma post oxidation, optimization of plasma post oxidation temperature and atomic Deuterium annealing were introduced. The reduction in interface roughness and interface states has effectively enhanced mobility in high Ns region.