Annette Bunker
Sally A. Mckee
Skip Abstract Section
Abstract
The advent of the system-on-chip and intellectual property hardware design paradigms makes protocol compliance verification increasingly important to the success of a project. One of the central tools in any verification project is the modeling language, and we survey the field of candidate languages for protocol compliance verification, limiting our discussion to languages originally intended for hardware and software design and verification activities. We frame our comparison by first constructing a taxonomy of these languages, and then by discussing the applicability of each approach to the compliance verification problem. Each discussion includes a summary of the development of the language, an evaluation of the language's utility for our problem domain, and, where feasible, an example of how the language might be used to specify hardware protocols. Finally, we make some general observations regarding the languages considered.
- Abarbanel, Y., Beer, I., Gluhovsky, L., Keidar, S., and Wolfsthal, Y. 2000. FoCs---Automatic generation of simulation checkers from formal specifications. In Computer Aided Verification, E. A. Emerson and A. P. Sistla, Eds. Lecture Notes in Computer Science, vol. 1855. Springer-Verlag, Berlin, Germany, 538--542.]] Google Scholar
- Accellera Organization, Inc. 2002. SystemVerilog 3.0: Accellera's Extensions to VerilogTM. Accellera Organization, Inc., Napa, CA.]]Google Scholar
- Accellera Organization, Inc. 2003. Property Specification Language Reference Manual. Accellera Organization, Inc., Napa, CA.]]Google Scholar
- Allara, A., Bombana, M., Cavalloro, P., Nevel, W., Putzke, W., and Radetzki, M. 1998. ATM cell modelling using objective VHDL. In Proceedings of Asia and South Pacific Design Automation Conference. 261--264.]]Google Scholar
- Alur, R., Etessami, K., and Yannakakis, M. 2000. Inference of message sequence charts. In Proceedings of the 22nd International Conference on Software Engineering. 304--313.]] Google Scholar
- Alur, R. and Yannakakis, M. 1999. Model checking of message sequence charts. In Proceedings of the Tenth International Conference on Concurrency Theory. Lecture Notes in Computer Science, vol. 1664. Springer-Verlag, Berlin, Germany, 114--129.]] Google Scholar
- Amla, N., Emerson, E. A., Kurshan, R. P., and Namjoshi, K. 2001. RTDT: A front-end for efficient model checking of synchronous timing diagrams. In Proceedings of Computer-Aided Verification. Lecture Notes in Computer Science, vol. 2102. Springer-Verlag, Berlin, Germany, 387--390.]] Google Scholar
- Amla, N., Emerson, E. A., Kurshan, R. P., and Namjoshi, K. S. 2000. Model checking synchronous timing diagrams. In Proceedings of the Third International Conference on Formal Methods in Computer-Aided Design, W. A. Hunt Jr. and S. D. Johnson, Eds. Lecture Notes in Computer Science, vol. 1954. Springer-Verlag, Berlin, Germany, 283--298.]] Google Scholar
- Amla, N., Emerson, E. A., Namjoshi, K., and Trefler, R. 2001. Assume-guarantee based compositional reasoning for synchronous timing diagrams. In Tools and Algorithms for the Construction and Analysis of Systems, T. Margaria and W. Yi, Eds. Lecture Notes in Computer Science, vol. 2031. Springer-Verlag, Berlin, Germany, 465--479.]] Google Scholar
- Amla, N., Emerson, E. A., and Namjoshi, K. S. 1999. Efficient decompositional model checking for regular timing diagrams. In Correct Hardware Design and Verification Methods: 10th IFIP WG10.5 Advanced Research Working Conference. Lecture Notes in Computer Science, vol. 1703. Springer-Verlag, Berlin, Germany, 465--479.]] Google Scholar
- Amla, N., Emerson, E. A., Namjoshi, K. S., and Trefler, R. J. 2002. Visual specifications for modular reasoning about asynchronous systems. In Formal Techniques for Networked and Distributed Systems. Lecture Notes in Computer Science, vol. 2529. Springer-Verlag, Berlin, Germany, 226--242.]] Google Scholar
- Amon, T., Borriello, G., Hu, T., and Liu, J. 1997. Symbolic timing verification of timing diagrams using Presburger formulas. In Proceedings of the 34th Design Automation Conference Proceedings. ACM Press, New York, NY, 226--231.]] Google Scholar
- André, C. 1996. Representation and analysis of reactive behaviors: A synchronous approach. Tech. rep. Laboratoire Informatique, Signaux, et Systémes, Université Nice-Sophia Antipolis, Sophia Antipolis, France.]]Google Scholar
- Armoni, R., Fix, L., Flaisher, A., Gerth, R., Ginsburg, B., Kanza, T., Landver, A., Mador-Haim, S., Singerman, E., Tiemeyer, A., Vardi, M. Y., and Zbar, Y. 2002. The ForSpec Temporal Logic: A new temporal property-specification language. In Tools and Algorithms for Construction and Analysis of Systems. Lecture Notes in Computer Science, vol. 2280. Springer-Verlag, Berlin, Germany, 296--211.]] Google Scholar
- Ashenden, P. J., Wilsey, P. A., and Martin, D. E. 1997. SUAVE: Painless extensions for an object-oriented VHDL. In VHDL International Users Forum Conference Proceedings.]] Google Scholar
- Baresi, L. 2002. Some preliminary hints on formalizing UML with object petri nets. In Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, H. Ehrig, B. J. Krämer, and A. Ertas, Eds. Society of Design and Process Science, 17. Website: www.sdpsnet.org.]]Google Scholar
- Beer, I., Ben-David, S., Eisner, C., Fisman, D., Gringauze, A., and Rodeh, Y. 2001. The temporal logic sugar. In Computer Aided Verification, G. Berry, H. Comon, and A. Finkel, Eds. Lecture Notes in Computer Science, vol. 2102. Springer-Verlag, Berlin, Germany, 363--367.]] Google Scholar
- Beer, I., Ben-David, S., Eisner, C., Geist, D., Gluhovsky, L., Heyman, T., Landver, A., Paanah, P., Rodeh, Y., Ronin, G., and Wolfsthal, Y. 1997. RuleBase: Model checking at IBM. In Computer Aided Verification, O. Grumberg, Ed. Lecture Notes in Computer Science, vol. 1254. Springer-Verlag, Berlin, Germany.]] Google Scholar
- Beer, I., Ben-David, S., Eisner, C., and Landver, A. 1996. RuleBase: An industry-oriented formal verification tool. In Proceeding of the 33rd Annual Conference on Design Automation. ACM Press, New York, NY, 655--660.]] Google Scholar
- Bell Labs Design Automation and Lucent Technologies. 1998. FormalCheck User's Guide, v2.1 ed. Bell Labs Design Automation and Lucent Technologies, Murray Hill, NJ.]]Google Scholar
- Bergeron, J. and Simmons, D. 2000. Exploiting the power of vera: Creating useful class libraries. In Proceedings of Synopsys Users Group.]]Google Scholar
- Berry, G. 1999. The Esterel v5 language primer. Tech. rep. Centre de Mathématiques Appliquées, Ecole des Mines and INRIA.]]Google Scholar
- Berry, G. 2000. The foundations of Esterel. In Proof, Language and Interaction: Essays in Honour of Robin Milner, G. Plotkin, C. Stirling, and M. Tofte, Eds. MIT Press, Cambridge, MA.]] Google Scholar
- Berry, G. and Kishinevsky, M. 2000. Hardware esterel language extension proposal. Tech. rep. Esterel Technologies, Mountain View, CA. Website: www.esterel-technologies.com/v3.]]Google Scholar
- Bhasker, J. 2002. A SystemC Primer. Star Galaxy Publishing, Alleutown, PA.]]Google Scholar
- Bianco, V. D., Lavazza, L., and Mauri, M. 2002. A formalization of UML Statecharts for real-time software modeling. In Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, H. Ehrig, B. J. Krämer, and A. Ertas, Eds. Society of Design and Process Science, 16. Website: www.sdpsnet.org.]]Google Scholar
- Bjesse, P., Claessen, K., Sheeran, M., and Singh, S. 1998. Lava: Hardware design in Haskell. In Proceedings of the Third ACM SIGPLAN International Conference on Functional Programming. ACM Press, New York, NY, 174--184.]] Google Scholar
- Blanc, L. and Dissoubray, S. 2000. Esterel Methodology for Complex System Design. In Proceedings of the International Summer School on Advance Microelectronics.]] Google Scholar
- Böger, E., Cavarra, A., and Riccobene, E. 2000. An ASM semantics for UML activity diagrams. In Algebraic Methodology and Software Technology, T. Rus, Ed. Lecture Notes in Computer Science, vol. 1816. Springer-Verlag, Berlin, Germany, 298--308.]] Google Scholar
- Bohn, J., Damm, W., Wittke, H., Klose, J., and Moik, A. 2002. Modeling and validating train system applications using statemate and live sequence charts. In Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, H. Ehrig, B. J. Krämer, and A. Ertas, Eds. Society for Design and Process Science, 34. Website: www.sdpsnet.org.]]Google Scholar
- Booch, G., Rumbaugh, J., and Jacobson, I. 1999. The Unified Modeling Language User Guide. Object Technology Series. Addison Wesley, Reading, MA.]] Google Scholar
- Bozga, B., Graf, S., Munier, L., Ober, I., Roux, J.-L., and Vincent, D. 2001. Timed extensions for SDL. In Proceedings of the Tenth SDL Forum. Lecture Notes in Computer Science, vol. 2078. Springer-Verlag, Berlin, Germany, 223--240.]] Google Scholar
- Bozga, M., Graf, S., Kerbrat, A., Vincent, D., Mounier, L., and Ober, I. 2000. SDL for real-time: What is missing? In Proceedings of SAM: 2nd Workshop on SDL and MSC. 108--122.]]Google Scholar
- Brat, G., Havelund, K., Park, S., and Visser, W. 2000. Java PathFinder---a second generation of a Java model checker. In Proceedigs of the Workshop on Advances in Verification.]]Google Scholar
- Brickford, M. and Guaspari, D. 1998. Lightweight analysis of UML. Tech. rep. Odyssey Research Associates, Ithaca, NY (now known as ATC-NY).]]Google Scholar
- Brunelli, M., Battú, L., Castelnuovo, A., and Sforza, F. 2001. Functional verification of a HW block using VERA. In Synopsys Users Group Proceedings.]]Google Scholar
- Bunker, A. and Gopalakrishnan, G. 2001. Using live sequence charts for hardware protocol specification and compliance verification. In Proceedings of the IEEE International High Level Design Validation and Test Workshop. IEEE Computer Society Press, Los Alamitos, CA, 95--100.]] Google Scholar
- Bunker, A. and Gopalakrishnan, G. 2002. Verifying a VCI bus interface model using an LSC-based specification. In Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, H. Ehrig, B. J. Krämer, and A. Ertas, Eds. Society of Design and Process Science, 48. Website: www.sdpsnet.org.]]Google Scholar
- Cabanis, D., Medhat, S., and Weavers, N. 1996. Object-oriented extensions of VHDL: The classification orientation. In VHDL User Forum. SIG-VHDL, 265--274.]]Google Scholar
- Claessen, K. and Sheeran, M. 2000. A tutorial on Lava: A hardware description and verification language. Tech. rep. School of Computer Science and Engineering, Chalmers University of Technology and Göteborg University, Göteborg, Sweden.]]Google Scholar
- Clark, T., Evans, A., Kent, S., and Sammut, P. 2001. The MMF approach to engineering object-oriented design languages. In Proceedings of the Workshop on Language Descriptions, Tools and Applications.]]Google Scholar
- Damm, W. and Harel, D. 2001. LSCs: Breathing life into message sequence charts. Form. Meth. Syst. Des. 19, 45--80.]] Google Scholar
- Damm, W. and Klose, J. 2001. Verification of a radio-based signaling system using the Statemate verification environment. Form. Meth. Syst. Des. 19, 121--141.]] Google Scholar
- Dömer, R. and Gajski, D. D. 1998. Comparison of the scenic design environment and the SpecC system. Tech. rep. Department of Information and Computer Science, University of California, Irvine, Irvine, CA.]]Google Scholar
- Dömer, R. and Gajski, D. D. 2000. Reuse and protection of intellectual property in the SpecC system. In Proceedings of Asia South Pacific Design Automation Conference. 49--54.]] Google Scholar
- Dömer, R., Gerstlauer, A., and Gajski, D. 2002. SpecC Language Reference Manual: Version 2.0. SpecC Technology Open Consortium, Tokyo, Japan. Website: http://www.SpecC.gr.jp/.]]Google Scholar
- Dömer, R., Zhu, J., and Gajski, D. D. 1998. The SpecC Language Reference Manual. Tech. rep. Department of Information and Computer Science, University of California, Irvine, Irvine, CA.]]Google Scholar
- Drechsler, R. and Groβe, D. 2002. Reachability analysis for formal verification of SystemC. In Proceedings of the Euromicro Symposium on Digital System Design. IEEE Computer Society, Press, Los Alamitos, CA, 337--340.]] Google Scholar
- Ellsberger, J., Hogrefe, D., and Sarma, A. 1997. SDL: Formal Object-Oriented Language for Communicating Systems. Prentice Hall, Englewood Cliffs, NJ.]]Google Scholar
- Fisler, K. 1996. A unified approach to hardware verification through a heterogeneous logic of design diagrams. Ph.D. dissertation, Indiana University, Bloomington, IN.]] Google Scholar
- Fisler, K. 1999. Timing diagrams: Formalization and algorthmic verification. J. Logic, Lang. Inform. 8, 3.]] Google Scholar
- Formal Methods Group. 2000. Guide to Sugar Formal Specification Language. IBM Haifa Research Laboratory, Haifa, Israel.]]Google Scholar
- Formal Methods Group. 2001. EDL. IBM Haifa Research Laboratory, Haifa, Israel.]]Google Scholar
- Fowler, M. 1999. UML Distilled. Object Technology Series. Addison-Wesley, Reading, MA.]]Google Scholar
- France, R., Bruel, J.-M., Larrondo-Petrie, M. M., and Shroff, M. 1997. Exploring the semantics of UML type structures with Z. In Proceedings of the Second IFIP Formal Methods in Object-Oriented and Distributed Systems (FMOODS). 247--260.]] Google Scholar
- Gajski, D. D., Zhu, J., Doemer, R., Gerstlauer, A., and Zhao, S. 1999. The SpecC Methodology. Tech. rep. ICS-99-56. Department of Information and Computer Science, University of California, Irvine, Irvine, CA.]]Google Scholar
- Gajski, D. D., Zhu, J., Dömer, R., Gerstlauer, A., and Zhao, S. 2000. SpecC: Specification Language and Methodology. Kluwer Academic Publishers, Dordrecht, The Netherlands.]]Google Scholar
- Goering, R. 2003. EDA divided on SystemVerilog. EE Times. (CMP Media. Website: www.eet.com.]]Google Scholar
- Gordon, M. J. C. 2002. Using HOL to study Sugar 2.0 semantics. In Track B Proceedings of the 15th International Conference on Theorem Proving in Higher Order Logics. Number CP-2002-211736. National Aeronautics and Space Administration, Washington, DC, 87--100.]]Google Scholar
- Gunter, E. L., Muscholl, A., and Peled, D. A. 2001. Compositional Message Sequence Charts. In Tools and Algorithms for the Construction and Analysis of Systems, T. Margaria and W. Yi, Eds. Lecture Notes in Computer Science, vol. 2031. Springer-Verlag, Berlin, Germany, 496--511.]] Google Scholar
- Harel, D. 1987. StateCharts: A visual formalism for complex systems. Sci. Comput. Programm. 8, 231--274.]] Google Scholar
- Harel, D. 2001. From play-in scenarios to code: An achievable dream. IEEE Comput. 34, 1 (Jan.), 53--60.]] Google Scholar
- Harel, D., Kugler, H., Marelly, R., and Pnueli, A. 2002. Smart play-out of behavioral requirements. In Formal Methods in Computer-aided Design. Lecture Notes in Computer Science, vol. 2517. Springer-Verlag, Berlin, Germany, 378--398.]] Google Scholar
- Harel, D. and Marelly, R. 2002. Playing with time: On the specification and execution of time-enriched LSCs. In Proceedings of the 10th IEEE/ACM International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems. IEEE Computer Society, Press, Los Alamitos, CA, 193--202.]] Google Scholar
- Harel, D., Pnueli, A., Schmidt, J. P., and Sherman, R. 1987. On the formal semantics of Statecharts. In IEEE Symposium On Logic In Computer Science. IEEE Computer Society Press, 54--64.]]Google Scholar
- Helaihel, R. and Olukotun, K. 1997. Java as a specification language for hardware-software systems. In Proceedings of the 1997 International Conference on Computer-Aided Design. 690--697.]] Google Scholar
- Helbig, J. and Kelb, P. 1994. An OBDD-representation of Statecharts. In Proceedings of the European Conference on Design Automation. IEEE Computer Society Press, 142--149.]]Google Scholar
- Henriksen, J. G., Mukun, M., Kumar, K. N., and Thiagarajan, P. 2000. On Message Sequence graphs and finitely generated regular MSC languages. In International Symposium on Mathematical Foundations of Computer Science. Lecture Notes in Computer Science, vol. 1853. Springer-Verlag, Berlin, Germany, 675--686.]] Google Scholar
- Hollander, Y., Noy, A., and Morley, M. 2001. The e Language: A fresh separation of concerns. In Proceedings Technology of Object-Oriented Languages and Systems (TOOLS 38 '01). IEEE Computer Society, Press, Los Alamitos, CA, 41--50.]] Google Scholar
- Hussmann, H. 2002. Loose semantics for UML/OCL. In Proceedings of the Sixth Biennial World Conference on Integrated Design and Process Technology, H. Ehrig, B. J. Krämer, and A. Ertas, Eds. Society of Design and Process Science, 15. Website: www.sdpsnet.org.]]Google Scholar
- International Telecommunication Union. 1998. ITU-T Recommendation Z.120: Message Sequence Chart (MSC)---Annex B: Formal Semantics of Message Sequence Charts. International Telecommunication Union, Genewa, Switzerland.]]Google Scholar
- International Telecommunication Union. 1999a. ITU-T Recommendation Z.100: Specification and Description Language (SDL). International Telecommunication Union, Genewa, Switzerland.]]Google Scholar
- International Telecommunication Union. 1999b. ITU-T Recommendation Z.120: Message Sequence Chart (MSC). International Telecommunication Union, Genewa, Switzerland.]]Google Scholar
- International Telecommunication Union. 2000a. ITU-T Recommendation Z.100: Specification and Description Language (SDL): Annex F1: SDL Formal Definition: General Overview. International Telecommunication Union, Genewa, Switzerland.]]Google Scholar
- International Telecommunication Union. 2000b. ITU-T Recommendation Z.100: Specification and Description Language (SDL): Annex F3: SDL Formal Definition: Dynamic Semantics. International Telecommunication Union, Genewa, Switzerland.]]Google Scholar
- James, P. and Dhamanwala, S. 2000. Vera, Vera on the wall: Useful lessons for first-time Vera users. In Proceedings of Synopsys Users Group.]]Google Scholar
- Kahn, G. 1974. The semantics of simple language for parallel programming. In IFIP Congress 1974. 471--475.]]Google Scholar
- Khordoc, K. 1996. Action diagrams: A methodology for the specification and verification of real-time systems. Ph.D. dissertation, McGill University, Montreal, P.Q., Canada.]]Google Scholar
- Khordoc, K. and Cerny, E. 1998. Semantics and verification of action diagrams with linear timing constraints. ACM Trans. Des. Automat. Electron. Syst. 3, 1, 21--60.]] Google Scholar
- Khordoc, K., Dufresne, M., and Cerny, E. 1991. A stimulus/response system based on hierarchical timing diagrams. In Proceedings of the IEEE International Conference on Computer-Aided Design. 358--361.]]Google Scholar
- Kim, S.-K. and Carrington, D. 1999. Formalizing the UML class diagram using Object-Z. In <<UML>>'99---The Unified Modeling Language: Beyond the Standard, R. France and B. Rumpe, Eds. Lecture Notes in Computer Science, vol. 1723. Springer-Verlag, Berlin, Germany, 83--98.]]Google Scholar
- Klose, J. and Wittke, H. 2001. An automata based interpretation of Live Sequence Charts. In Tools and Algorithms for the Construction and Analysis of Systems, T. Margaria and W. Yi, Eds. Lecture Notes in Computer Science, vol. 2031. Springer-Verlag, Berlin, Germany, 512--527.]] Google Scholar
- Krishnamoorthy, S., Arora, G., and Guravannavar, R. 2002. Network system verification with VERA. In Proceedings of Synopsys Users Group.]]Google Scholar
- Krüger, I., Grosu, R., Scholz, P., and Broy, M. 1999. From MSCs to Statecharts. In Distributed and Parallel Embedded Systems. Kluwer Academic Publishers, Dordrecht, The Netherlands.]]Google Scholar
- Kuhn, T., Oppold, T., Winterholer, M., Rosenstiel, W., Edwards, M., and Kashai, Y. 2001. A framework for object oriented hardware specification, verification, and synthesis. In Proceedings of the 38th Design Automation Conference. ACM Press, New York, NY, 413--418.]] Google Scholar
- Kuhn, T. and Rosenstiel, W. 1998. Java based modeling and simulation of digital systems on register transfer level. In Proceedings of the Workshop on System Design Automation.]]Google Scholar
- Kuhn, T., Rosenstiel, W., and Kebschull, U. 1999. Description and simulation of hardware/software systems with Java. In Proceedings of the 36th Design Automation Conference. ACM Press, New York, NY, 790--793.]] Google Scholar
- Levin, V. and Yenigün, H. 2001. SDLcheck: A model checking tool. In Computer Aided Verification, G. Berry, H. Comon, and A. Finkel, Eds. Lecture Notes in Computer Science, vol. 2102. Springer-Verlag, Berlin, Germany, 378--381.]] Google Scholar
- Lüth, K., Neihaus, J., and Peikenkamp, T. 1998. HW/SW cosynthesis using Statecharts and symbolic timing diagrams. In International Workshop on Rapid System Prototyping. IEEE Computer Society, Press, Los Alamitos, CA, 212--217.]] Google Scholar
- Lüttgen, G., von der Beeck, M., and Cleaveland, R. 2000. A compositional approach to Statecharts semantics. In Technical Report of ICASE, NASA Langley Research Center, Hampton, VA. ICASE Rep. No. 2000-12, NASA/CR-2000-210086, NASA Langley Research Center, Hampton, VA.]] Google Scholar
- Madhusudan, P. 2001. Resoning about sequential and branching behaviors of Message Sequence Graphs. In International Colloquium on Automata, Languages, and Programming, F. Orejas, P. Spirakis, and J. van Leeuwen, Eds. Lecture Notes in Computer Science, vol. 2076. Springer-Verlag, Berlin, Germany, 809--820.]] Google Scholar
- Madhusudan, P. and Meenakshi, B. 2001. Beyond Message Sequence Graphs. In Foundations of Software Technology and Theoretical Computer Science, R. Hariharan, M. Mukund, and V. Vinay, Eds. Lecture Notes in Computer Science, vol. 2245. Springer-Verlag, Berlin, Germany, 256--267.]] Google Scholar
- Monaco, J., Holloway, D., and Raina, R. 1996. Functional verification methodology for the PowerPC microprocessor. In Proceedings of the 33rd Design Automation Conference. 319--324.]] Google Scholar
- Moorby, P., Salz, A., Flake, P., Dudani, S., and Fitzpatrick, T. 2003. Achieving determinism in SystemVerilog 3.1 scheduling semantics. In Proceedings of the Design and Verification Conference.]]Google Scholar
- Mueller, W., Dömer, R., and Gerstlauer, A. 2002. The formal execution semantics of SpecC. In Proceedings of the 15th International Symposium on Systems Synthesis. 150--155.]] Google Scholar
- Mueller, W., Ruf, J., Hoffmann, D., Gerlach, J., Kropf, T., and Rosenstiehl, W. 2001. The Simulation Semantics of SystemC. In Proceedings of the Conference on Design Automation and Test in Europe. 64--70.]] Google Scholar
- Muscholl, A. and Peled, D. 1999. Message Sequence Graphs and decision {problems on Mazurkiewicz traces. In International Symposium on Mathematical Foundations of Computer Science. Lecture Notes in Computer Science, vol. 1672. Springer-Verlag, Berlin, Germany, 81--91.]] Google Scholar
- Muscholl, A. and Peled, D. 2000. Analyzing Message Sequence Charts. In Proceedings of the SDL and MSC Workshop.]]Google Scholar
- Muscholl, A. and Peled, D. 2001. From finite state communication protocols to high-level Message Sequence Charts. In International Symposium on Mathematical Foundations of Computer Science. Lecture Notes in Computer Science, vol. 2076. Springer-Verlag, Berlin, Germany, 720--731.]] Google Scholar
- Muscholl, A., Peled, D., and Su, Z. 1998. Deciding properties for Message Sequence Charts. In Foundations of Software Science and Compuation Structures. Lecture Notes in Computer Science, vol. 1378. Springer-Verlag, Berlin, Germany, 226--242.]] Google Scholar
- Open SystemC Initiative. 1999. Website: www.systemc.org.]]Google Scholar
- Pnueli, A. and Shalev, M. 1991. What is in a step: On the semantics of Statecharts. In Theoretical Aspects of Computer Software, T. Ito and A. R. Meyer, Eds. Lecture Notes in Computer Science, vol. 526. Springer-Verlag, Berlin, Germany, 244--264.]] Google Scholar
- Putzke-Röming, W., Radetzki, M., and Nebel, W. 1998. A flexible message passing mechanism for Objective VDHL. In Proceedings of the Conference on Design Automation and Test in Europe. 242--249.]] Google Scholar
- Radetzki, M., Putzke, W., Nebel, W., Maginot, S., Berge, J.-M., and Tagant, A.-M. 1997. VHDL language extensions to support abstraction and re-use. In Proceedings of the Workshop on Libraries, Component Modeling and Quality Assurance.]]Google Scholar
- Richters, M. and Gogolla, M. 1998. On formalizing the UML Object Constraint Language OCL. In Proceedings of the 17th Interantional Conference on Conceptual Modeling, T.-W. Ling, S. Ram, and M. L. Lee, Eds. Lecture Notes in Computer Science, vol. 1507. Springer-Verlag, Berlin, Germany, 449--464.]] Google Scholar
- Richters, M. and Gogolla, M. 2001. OCL---syntax, semantics and tools. In Advances in Object Modelling with the OCL, T. Clark and J. Warmer, Eds. Lecture Notes in Computer Science, vol. 2263. Springer-Verlag, Berlin, Germany, 43--69.]] Google Scholar
- Rumbaugh, J., Jacobson, I., and Booch, G. 1999. The Unified Modeling Language Reference Manual. Object Technology Series. Addison-Wesley Longman, Inc., Reading, MA.]] Google Scholar
- Santarini, M. 2001. Deal links formal verification to testbench generation. EE Times. (CMP Media Website: www.eet.com.)]]Google Scholar
- Sharygina, N., Browne, J. C., and Kurshan, R. P. 2001. A formal object-oriented analysis for software reliability: Design for verification. In Fundamental Approaches to Software Engineering, H. Hussmann, Ed. Lecture Notes in Computer Science, vol. 2029. Springer-Verlag, Berlin, Germany, 318--333.]] Google Scholar
- Shimizu, K. and Dill, D. L. 2002. Deriving a simulation input generator and a coverage metric from a formal specification. In Proceedings of the 39th Design Automation Conference. ACM Press, New York, NY, 801--806.]] Google Scholar
- Shimizu, K., Dill, D. L., and Chou, C.-T. 2001. A specification methodology by a collection of compact properties as applied to the Intel® ItaniumTM processor bus protocol. In Correct Hardware Design and Verification Methods: 11th IFIP WG10.5 Advanced Research Working Conference. Lecture Notes in Computer Science, vol. 2114. Springer-Verlag, Berlin, Germany, 340--354.]] Google Scholar
- Shimizu, K., Dill, D. L., and Hu, A. J. 2000. Monitor-based formal specification of PCI. In Formal Methods in Computer-Aided Design, W. A. Hunt Jr. and S. D. Johnson, Eds. Lecture Notes in Computer Science, vol. 1954. Springer-Verlag, Berlin, Germany, 335--352.]] Google Scholar
- Sutherland, S. 2002. Verilog, the next generation: Accellera's systemVerilog. In Proceedings of the HDL Conference.]]Google Scholar
- Sutherland, S. 2003. SystemVerilog 3.1: It's what the DAVEs in your company asked for. In Proceedings of the Design and Verification Conference.]]Google Scholar
- Swamy, S., Molin, A., and Covnot, B. 1995. OO-VHDL: Object-oriented extensions to VHDL. IEEE Comput. 28, 10, 18--26.]] Google Scholar
- Swan, S. 2001. An introduction to system level modeling in SystemC 2.0. Tech. rep. Open SystemC Initiative. Website: www.systemc.org.]]Google Scholar
- Synopsys, Inc. 2001a. OpenVera 1.01: Language Reference Manual. Synopsys, Inc., Mountain View, CA. Website: www.synopsys.com.]]Google Scholar
- Synopsys, Inc. 2001b. OpenVera technology backgrounder. Synopsys, Inc., Mountain View, CA. Website: www.synopsys.com.]]Google Scholar
- Synopsys, Inc. 2002. OpenVeraTM Assertions (OVA) and ForSpec. Synopsys, Inc., Mountain View, CA. Website: www.synopsys.com.]]Google Scholar
- Tanenbaum, A. 1998. Computer Networks. Prentice Hall, Englewood Cliffs, NJ.]] Google Scholar
- The Object Management Group. 1999. OMG Unified Modeling Language Specification. The Object Management Group, Needham, MA.]]Google Scholar
- Thompson, K. and Williamson, L. 2002. Hardware verification with the Unified Modeling Language and Vera. In Proceedings of Synopsys Users Group.]]Google Scholar
- Verisity Design, Inc. 1999. Spec-based verification. Verisity Design, Mountain View, CA.]]Google Scholar
- Visser, W., Havelund, K., Brat, G., and Park, S. 2000. Model checking programs. In Proceedings of the International Conference on Automated Software Engineering.]] Google Scholar
- Walkup, E. A. and Borriello, G. 1994. Interface timing verification with application to synthesis. In Proceedings of the 31st Design Automation Conference. ACM Press, New York, NY, 106--112.]] Google Scholar
- Wang, R. and Wen, Z. 2002. A verification environment for PCI-X BFMs in VERA. In Proceedings of Synopsys Users Group.]]Google Scholar
- Warmer, J. and Kleppe, A. 2000. The Object Constraint Language: Precise Modeling with UML. Addison-Wesley Longman, Inc., Boston, MA.]] Google Scholar
- Young, J., MacDonald, J., Shilman, M., Tabbara, P., and Newton, A. 1998. Design and specification of embedded systems in Java using sucessive, formal refinement. In Proceedings of the 35th Design Automation Conference. ACM Press, New York, NY, 70--75.]] Google Scholar
- Zippelius, R. and Müller-Glaser, K. D. 1992. An object-oriented extension of VHDL. In Proceedings of the VHDL Forum for Computer Aided Design in Europe. 155--163.]]Google Scholar
Index Terms
- Formal hardware specification languages for protocol compliance verification
Recommendations
A Comparison of C/C++-based Software/Hardware Co-design Description Languages
ICYCS '08: Proceedings of the 2008 The 9th International Conference for Young Computer ScientistsMany description languages are used in hardware/software co-design of embedded systems. This paper presents the programming characteristics, structure peculiarities and design flow of three kinds of co-design description language based on C/C++: SystemC,...
ESys.Net: a new solution for embedded systems modeling and simulation
LCTES '04The next generation of tools for embedded systems design will represent a common arena for several cooperating groups. These tools will permit system design at a high abstraction level and enable automatic refinement through several abstraction levels ...
From Statecharts to Verilog: a formal approach to hardware/software co-specification
AbstractHardware/software co-specification is a critical phase in co-design. Our co-specification process starts with a high level graphical description in Statecharts and ends with an equivalent parallel composition of hardware and software descriptions ...
Reviews
Festus Gail Gray
Formal specification languages that are candidates for interface standard compliance verification are surveyed in this paper. After constructing a taxonomy of candidate languages, the authors discuss the applicability of each language to the compliance verification problem, using four desirable criteria: precise semantics, short learning curve, potential for automatic verification, and ease of integration with existing design practice. The same common example, a simple handshaking protocol, is implemented in most of the languages to illustrate similarities and differences among the languages. The authors conclude that the growing complexity of the verification problem is outpacing the growth in power of current languages, and that specification languages must adapt to meet the new demands. The paper includes an impressive bibliography of current languages with verification potential. This paper will be of particular interest to practitioners who face the selection of a tool suite to address verification issues, and will provide background information for specialists and nonspecialists who are interested in the design and verification field. Online Computing Reviews Service
Access critical reviews of Computing literature here
Become a reviewer for Computing Reviews.
Comments