Rahul M. Rao
ABSTRACT
Gate leakage current is expected to be the dominant leakage component in future technology generations. In this paper, we propose methods for steady-state gate leakage estimation based on state characterization. An efficient technique for pattern-dependent gate leakage estimation is presented. Further, we propose the use of this technique for estimating the average gate leakage of a circuit using pattern-independent probabilistic analysis. Results on a large set of benchmark ISCAS circuits show an accuracy within 5% of SPICE results with 500X to 50000X speed improvement.
- International Technology Roadmap for SemiConductors, http://public.itrs.net/Files/2001ITRS/Home.html.Google Scholar
- R. Langevelde, A. Scholten, R. Duffy, F. Cubaynes, M. Knitel and D. Klaassen, "Gate current: Modeling, Extraction and impact on RF performance,"Google Scholar
- Y.C. Yeo, et.al, "Direct Tunneling Gate Leakage Current in Transistors with Ultrathin Silicon Nitride Gate Dielectric," IEEE Electron Device Letters, vol. 21, no. 11, pp. 540--542, Nov. 2000.Google ScholarCross Ref
- C. T. Chuang and R. Puri, "Effects of Gate-to-Body Tunneling Current on Pass-Transistor Based PD/SOI CMOS Circuits," IEEE Intnl. SOI Conf., pp. 121--122, Oct. 2002.Google Scholar
- C. Choi, K. Nam, Z. Yu and R. Dutton, "Impact of Gate Direct Tunneling Current on Circuit Performance: A Simulation Study," IEEE Trans. on Electron Devices, vol. 48, no. 12, pp. 2823--2829, Dec. 2001.Google ScholarCross Ref
- F. Hamzaoglu and M. Stan, "Circuit-Level Techniques to Control Gate Leakage for sub-100nm CMOS," Proc. ISLPED, pp. 60--63, Aug. 2002. Google ScholarDigital Library
- K. Yang, et.al, "Edge Hole Direct Tunneling Leakage in Ultrathin Gate Oxide p-Channel MOSFETs," IEEE Trans. on Electron Devices, vol. 48, no. 12, pp. 2790--2795, Dec. 2001.Google ScholarCross Ref
- E. Acar, et.al, "Leakage and Leakage Computation Analysis for Combinational Circuits," Proc. ISLPED, Aug. 2003. Google ScholarDigital Library
Index Terms
- Efficient techniques for gate leakage estimation
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