Jongsun Park
ABSTRACT
We present a high performance and low power FIR filter design, which is based on computation sharing multiplier (CSHM). CSHM specifically targets computation re-use in vector-scalar products and is effectively used in our FIR filter design. Efficient circuit level techniques: a new carry select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. The proposed FIR filter architecture was implemented in 0.25 μm technology. Experimental results on a 10 tap low pass CSHM FIR filter show speed and power improvement of 19% and 17%, respectively, with respect to an FIR filter based on Wallace tree multiplier.
- K. Muhammad, "Algorithmic and Architectural Techniques for Low Power Digital Signal Processing," Ph.D. thesis, Purdue University, 1999. Google Scholar
Digital Library
- J. Park, H. Choo, K. Muhammad, K. Roy, " Non adaptive and Adaptive filter implementation based on sharing multiplication," ICASSP, June 2000. Google ScholarDigital Library
- Jan M. Rabaey, "Digital Integrated Circuits : A Design Perspective," Prentice Hall, New Jersey, 1996. Google ScholarDigital Library
- H. Samueli, "An improved Search Algorithm for the Design of Multiplierless FIR filter with Powers-of-Two Coefficients," IEEE Trans. On circuits and systems, Vol. 36, No. 7, pp. 1044--1047, Jul. 1989.Google ScholarCross Ref
- S. White, "Applications of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review," IEEE ASSP Magazine, July 1989, pp. 4--19.Google ScholarCross Ref
- W. Jeong, K, Roy, and C. Koh. "High-Performance Low-Power Carry Select Adder using Dual Transition Skwed Logic," ESSCIRC, 2001 Google ScholarDigital Library
- G. Gerosa et al., "A 2.2 W 80 MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 29, pp. 1440--1452, Dec. 1994Google ScholarCross Ref
- H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in Int. Solid-State Circuits Conference, Dig. of Tech. Papers, Feb. 1996, pp. 138--139Google Scholar
- F. Klass, "Semi-dynamic and dynamic flip-flops with embedded logic," in Symp. on VLSI Circuits, Dig. of Tech. Papers, June 1998, pp. 108--109.Google Scholar
- B. Nikolic et al., "Sense amplifier-based flip-flop," in Int. Solid-State Circuits Conf., Dig. of Tech. Papers, Feb. 1999, pp. 282--283Google Scholar
- B. S. Kong et al., "Conditional Capture Flip-Flop for Statistical Power Reduction," in ISSCC Dig. Tech. Papers, pp. 290--291, Feb. 2000Google Scholar
- H. Partovi, "Clocked storage elements," in Chandrakasan, A., Bowhill, W.J., and Fox, F. (eds.). Design of High-Performance Microprocessor Circuits. IEEE Press, Piscataway NJ, 2000, 207--23.Google Scholar
Index Terms
- High performance and low power FIR filter design based on sharing multiplication
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