Abstract
Routing is a crucial step in Field Programmable Gate Array (FPGA) physical design, as it determines the routes of signals in the circuit, which impacts the design implementation quality significantly. It can be very time-consuming to successfully route all the signals of large circuits that utilize many FPGA resources. Attempts have been made to shorten the routing runtime for efficient design exploration while expecting high-quality implementations. In this work, we elaborate on the connection-based routing strategy and algorithmic enhancements to improve the serial FPGA routing. We also explore a recursive partitioning-based parallelization technique to further accelerate the routing process. To exploit more parallelism by a finer granularity in both spatial partitioning and routing, a connection-aware routing bounding box model is proposed for the source-sink connections of the nets. It is built upon the location information of each connection’s source, sink, and the geometric center of the net that the connection belongs to, different from the existing net-based routing bounding box that covers all the pins of the entire net. We present that the proposed connection-aware routing bounding box is more beneficial for parallel routing than the existing net-based routing bounding box. The quality and runtime of the serial and multi-threaded routers are compared to the router in VPR 7.0.7. The large heterogeneous Titan23 designs that are targeted to a detailed representation of the Stratix IV FPGA are used for benchmarking. With eight threads, the parallel router using the connection-aware routing bounding box model reaches a speedup of 6.1× over the serial router in VPR 7.0.7, which is 1.24× faster than the one using the existing net-based routing bounding box model, while reducing the total wire-length by 10% and the critical path delay by 7%.
- Vaughn Betz and Jonathan Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications (FPL’97). 213--222. Google ScholarDigital Library
- Vaughn Betz and Jonathan Rose. 1999. FPGA routing architecture: Segmentation and buffering to optimize speed and density. In Proceedings of the ACM/SIGDA 7th International Symposium on Field Programmable Gate Arrays (FPGA’99). 59--68. Google ScholarDigital Library
- X. Chen, J. Zhu, and M. Zhang. 2011. Timing-driven routing of high fanout nets. In Proceedings of the 21st International Conference on Field Programmable Logic and Applications. 423--428. Google ScholarDigital Library
- M. Gort and J. H. Anderson. 2012. Accelerating FPGA routing through parallelization and engineering enhancements special section on PAR-CAD 2010. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 31, 1 (2012), 61--74. Google ScholarDigital Library
- M. Gort and J. H. Anderson. 2013. Combined architecture/algorithm approach to fast FPGA routing. IEEE Trans. Very Large Scale Integr. Syst. 21, 6 (2013), 1067--1079. Google ScholarDigital Library
- C. H. Hoo, Y. Ha, and A. Kumar. 2016. ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. In Proceedings of the 26th International Conference on Field Programmable Logic and Applications (FPL’16). 1--11.Google Scholar
- Chin Hau Hoo and Akash Kumar. 2018. ParaDRo: A parallel deterministic router based on spatial partitioning and scheduling. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’18). 67--76. Google ScholarDigital Library
- Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Anderson, Jonathan Rose, and Vaughn Betz. 2014. VTR 7.0: Next generation architecture and CAD system for FPGAs. ACM Trans. Reconfig. Technol. Syst. 7, 2, Article 6 (July 2014), 30 pages. Google ScholarDigital Library
- Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Ye, Wei Mark Fang, Kenneth Kent, and Jonathan Rose. 2011. VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfig. Technol. Syst. 4, 4, Article 32 (Dec. 2011), 23 pages. Google ScholarDigital Library
- L. McMurchie and C. Ebeling. 1995. PathFinder: A negotiation-based performance-driven router for FPGAs. In Proceedings of the 3rd International ACM Symposium on Field-Programmable Gate Arrays. 111--117. Google ScholarDigital Library
- Y. Moctar, M. Stojilović, and P. Brisk. 2018. Deterministic parallel routing for FPGAs based on Galois parallel execution model. In Proceedings of the 28th International Conference on Field Programmable Logic and Applications (FPL’18). 21--25.Google Scholar
- Y. O. M. Moctar and P. Brisk. 2014. Parallel FPGA routing based on the operator formulation. In Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC’14). 1--6. Google ScholarDigital Library
- Kevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, and Vaughn Betz. 2015. Timing-driven titan: Enabling large benchmarks and exploring the gap between academic and commercial CAD. ACM Trans. Reconfig. Technol. Syst. 8, 2, Article 10 (Mar. 2015), 18 pages. Google ScholarDigital Library
- Minghua Shen and Guojie Luo. 2015. Accelerate FPGA routing with parallel recursive partitioning. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’15). 118--125. Google ScholarDigital Library
- Minghua Shen and Guojie Luo. 2017. Corolla: GPU-accelerated FPGA routing based on subgraph dynamic expansion. In Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA’17). 105--114. Google ScholarDigital Library
- M. Shen and N. Xiao. 2018. Fine-grained parallel routing for FPGAs with selective expansion. In Proceedings of the IEEE 36th International Conference on Computer Design (ICCD’18). 577--586.Google Scholar
- M. Shen and N. Xiao. 2018. Load balance-aware multi-core parallel routing for large-scale FPGAs. In Proceedings of the IEEE 36th International Conference on Computer Design (ICCD’18). 595--602.Google Scholar
- Jordan S. Swartz, Vaughn Betz, and Jonathan Rose. 1998. A fast routability-driven router for FPGAs. In Proceedings of the ACM/SIGDA 6th International Symposium on Field Programmable Gate Arrays (FPGA’98). 140--149. Google ScholarDigital Library
- Elias Vansteenkiste. 2016. New FPGA Design Tools and Architectures. Ph.D. Dissertation. Ghent University.Google Scholar
- E. Vansteenkiste, K. Bruneel, and D. Stroobandt. 2013. A connection-based router for FPGAs. In Proceedings of the International Conference on Field-Programmable Technology (FPT’13). 326--329.Google Scholar
- D. Vercruyce, E. Vansteenkiste, and D. Stroobandt. 2018. How preserving circuit design hierarchy during FPGA packing leads to better performance. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 37, 3 (2018), 629--642.Google ScholarCross Ref
- D. Vercruyce, E. Vansteenkiste, and D. Stroobandt. 2019. CRoute: A fast high-quality timing-driven connection-based FPGA router. In Proceedings of the IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM’19). 53--60.Google Scholar
- D. Wang, Z. Duan, C. Tian, B. Huang, and N. Zhang. 2018. A runtime optimization approach for FPGA routing. IEEE IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 37, 8 (2018), 1706--1710.Google ScholarCross Ref
- D. Wang, Z. Duan, C. Tian, B. Huang, and N. Zhang. 2020. ParRA: A shared memory parallel FPGA router using hybrid partitioning approach. IEEE Trans. Comput.-Aided Design Integr. Circ. Syst. 39, 4 (2020), 830--842.Google ScholarCross Ref
- C. Zhu, J. Wang, and J. Lai. 2013. A novel net-partition-based multithread FPGA routing method. In Proceedings of the 23rd International Conference on Field programmable Logic and Applications. 1--4.Google Scholar
Index Terms
- Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization
Recommendations
Wire type assignment for FPGA routing
FPGA '03: Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arraysThe routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently developed FPGAs (e.g., Virtex-II), there are more versatile wire types and ...
Accelerating FPGA Routing Through Parallelization and Engineering Enhancements Special Section on PAR-CAD 2010
We present parallelization and heuristic techniques to reduce the run-time of field-programmable gate array (FPGA) negotiated congestion routing. Two heuristic optimizations provide over $3\times$ speedup versus a sequential baseline. In our parallel ...
Multiterminal net routing for partial crossbar-based multi-FPGA systems
Special section on system-level interconnect prediction (SLIP)Multi-FPGA (field-programmable gate arrays) systems are used as custom computing machines to solve compute-intensive problems and also in the verification and prototyping of large circuits. In this paper, we address the problem of routing multiterminal ...
Comments