ABSTRACT
As throughput of computer networks is on a constant rise, there is a need for ever-faster packet parsing modules at all points of the networking infrastructure. Parsing is a crucial operation which has an influence on the final throughput of a network device. Moreover, this operation must precede any kind of further traffic processing like filtering/classification, deep packet inspection, and so on. This paper presents a parser architecture which is capable to currently scale up to a terabit throughput in a single FPGA, while the overall processing speed is sustained even on the shortest frame lengths and for an arbitrary number of supported protocols. The architecture of our parser can be also automatically generated from a high-level description of a protocol stack in the P4 language which makes the rapid deployment of new protocols considerably easier. The results presented in the paper confirm that our automatically generated parsers are capable of reaching an effective throughput of over 1 Tbps (or more than 2000 Mpps) on the Xilinx UltraScale+ FPGAs and around 800 Gbps (or more than 1200 Mpps) on their previous generation Virtex-7 FPGAs.
- M. Attig and G. Brebner. 2011. 400 Gb/s Programmable Packet Parsing on a Single FPGA. In Architectures for Networking and Communications Systems (ANCS), 2011 Seventh ACM/IEEE Symposium on. 12--23. Google ScholarDigital Library
- P. Benáček, V. Puš, and H. Kubátová. 2016. P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). 148--155.Google Scholar
- L. Kekely, J. Kořenek, and V. Puš. 2012. Low-latency Modular Packet Header Parser for FPGA. In Proceedings of the Eighth ACM/IEEE Symposium on Architectures for Networking and Communications Systems. ACM, New York, NY, USA, 77--78. Google ScholarDigital Library
- L. Kekely, V. Puš, and J. Kořenek. 2014. Design Methodology of Configurable High Performance Packet Parser for FPGA. In 17th IEEE Symposium on Design and Diagnostics of Electronic Circuits&Systems. IEEE Computer Society, 189--194.Google Scholar
- P. Kobierský, J. Kořenek, and L. Polčák. 2009. Packet header analysis and field extraction for multigigabit networks. In Proceedings of the 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits&Systems (DDECS). IEEE Computer Society, Washington, USA, 96--101. Google ScholarDigital Library
- C. Kozanitis, J. Huber, S. Singh, and G. Varghese. 2010. Leaping Multiple Headers in a Single Bound: Wire-Speed Parsing Using the Kangaroo System. In Proceedings of the 29th Conference on Information Communications. Google ScholarDigital Library
- P. Bosshart et al. 2014. P4: Programming Protocol-independent Packet Processors. SIGCOMM Computer Communication Review 44, 3 (July 2014), 87--95. Google ScholarDigital Library
- The P4 Language Consortium. 2017. The P4 Language Specification. (24 May 2017). https://p4lang.github.io/p4-spec/p4--14/v1.0.4/tex/p4.pdfGoogle Scholar
- The P4 Language Consortium. 2017. P416 Language Specification. (22 May 2017). https://p4lang.github.io/p4-spec/docs/P4--16-v1.0.0-spec.pdfGoogle Scholar
- H. Wang, R. Soulé, H. T. Dang, K. S. Lee, V. Shrivastav, N. Foster, and H. Weatherspoon. 2017. P4FPGA: A Rapid Prototyping Framework for P4. In Proceedings of the Symposium on SDN Research (SOSR '17). ACM, New York, NY, USA, 122--135. Google ScholarDigital Library
Index Terms
- Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput
Recommendations
The P4->NetFPGA Workflow for Line-Rate Packet Processing
FPGA '19: Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysP4 has emerged as the de facto standard language for describing how network packets should be processed, and is becoming widely used by network owners, systems developers, researchers and in the classroom. The goal of the work presented here is to make ...
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs
FPGA '18: Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysPacket parsing is a key step in SDN-aware devices. Packet parsers in SDN networks need to be both reconfigurable and fast, to support the evolving network protocols and the increasing multi-gigabit data rates. The combination of packet processing ...
An efficient packet parser architecture for software-defined 5G networks
AbstractSoftware-defined networks (SDN) has emerged with the capability to program in order to enhance flexibility, management, and testing of new ideas in the next generation of networks by removing current network limitations. Network ...
Comments