Yau-Tsun Steven Li
Abstract
Embedded systems generally interact in some way with the outside world. This may involve measuring sensors and controlling actuators, communicating with other systems, or interacting with users. These functions impose real-time constraints on system design. Verification of these specifications requires computing an upper bound on the worst-case execution time (WCET) of a hardware/software system. Furthermore, it is critical to derive a tight upper bound on WCET in order to make efficient use of system resources.
The problem of bounding WCET is particularly difficult on modern processors. These processors use cache-based memory systems that vary memory access time based on the dynamic memory access pattern of the program. This must be accurately modeled in order to tightly bound WCET. Several analysis methods have been proposed to bound WCET on processors with instruction caches. Existing approaches either search all possible program paths, an intractable problem, or they use highly pessimistic assumptions to limit the search space. In this paper we present a more effective method for modeling instruction cache activity and computing a tight bound on WCET. The method uses an integer linear programming formulation and does not require explicit enumeration of program paths. The method is implemented in the program cinderella and we present some experimental results of this implementation.
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Index Terms
- Performance estimation of embedded software with instruction cache modeling
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Reviews
Maurice S. Elzas
The design of embedded systems differs from the design of other computer systems mainly in that, while an embedded system will often use the same components as a standard PC, it will do so in an environment with very little user control and will be focused on a single application. Moreover, the system's importance to the environment in which it is embedded will require optimal, uninterrupted operation and minimum size and cost. This is an elaborate and well-researched paper on one of the key problems confronting the designers of embedded systems. The processors used in embedded systems are similar to those used in ordinary computers, and some components that are generally most welcome can cause design problems when used in embedded systems. A case in point is the presence of caches, for instructions as well as for data. The optimal design problem is complicated further by the fact that, although the system runs a single application, its behavior will be greatly influenced by the data it acquires from the outside world. Optimal design in this case means the fastest execution combined with the smallest size and lowest cost for the desired reliability. It is obvious that such a design cannot be assessed without extensive testing. While this may be physically possible for simple systems with small applications, the task will become daunting for larger, more complex situations. In such cases, an accurate mathematical model, focused on the instruction cache problem, for establishing the worst-case execution time of the system being designed can provide an answer to the dilemma. The authors clearly present the mathematical background of their approach and illustrate its power with a reasonable number of example experiments. A sound list of references concludes the paper. The paper is not intended for either the faint-hearted or inexperienced reader, nor for the designer concerned with relatively simple systems. However, readers who are concerned with the design of more ambitious embedded systems can glean many useful ideas and techniques from this text.
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