Rajdeep Mukherjee
ABSTRACT
Verification is indispensable for building reliable of hardware/software co-designs. However, the scope of formal methods in this domain is limited. This is attributed to the lack of unified property specification languages, the semantic gap between hardware and software components, and the lack of verifiers that support both C and Verilog/VHDL. To address these limitations, we present an approach that uses a bounded co-verification tool, HW-CBMC, for formally validating hardware/software co-designs written in Verilog and C. Properties are expressed in C enriched with special-purpose primitives that capture temporal correlation between hardware and software events. We present an industrial case-study, proving bounded safety properties as well as discovering critical co-design bugs on a large and complex text analytics FPGA accelerator from IBM®.
- S. Ahn and S. Malik. Automated firmware testing using firmware-hardware interaction patterns. In CODES+ISSS, pages 1--25, 2014. Google Scholar
Digital Library
- L. De Moura and N. Bjørner. Z3: An efficient SMT solver. In TACAS, pages 337--340. Springer-Verlag, 2008. Google ScholarDigital Library
- N. Eén and A. Biere. Effective preprocessing in SAT through variable and clause elimination. In SAT, pages 61--75, 2005. Google ScholarDigital Library
- H. Giefers, R. Polig, and C. Hagleitner. Accelerating arithmetic kernels with coherent attached FPGA coprocessors. In DATE, pages 1072--1077, 2015. Google ScholarDigital Library
- D. Große, U. Kühne, and R. Drechsler. HW/SW co-verification of embedded systems using bounded model checking. In GLSVLSI, pages 43--48, 2006. Google ScholarDigital Library
- A. Horn, M. Tautschnig, C. G. Val, L. Liang, T. Melham, J. Grundy, and D. Kroening. Formal co-validation of low-level hardware/software interfaces. In FMCAD, pages 121--128, 2013.Google ScholarCross Ref
- D. Kroening, E. Clarke, and K. Yorav. Behavioral consistency of C and Verilog programs using bounded model checking. In DAC, pages 368--371, 2003. Google ScholarDigital Library
- J. Li, F. Xie, T. Ball, V. Levin, and C. McGarvey. An automata-theoretic approach to hardware/software co-verification. In FASE, pages 248--262, 2010. Google ScholarDigital Library
- F. Lugou, L. Apvrille, and A. Francillon. Toward a Methodology for Unified Verification of Hardware/Software Co-designs. Journal of Cryptographic Engineering, pages 1--12, 2016.Google Scholar
- Y. Mahajan, C. Chan, A. Bayazit, S. Malik, and W. Qin. Verification driven formal architecture and microarchitecture modeling. In MEMOCODE, pages 123--132, 2007. Google ScholarDigital Library
- D. Monniaux. Verification of device drivers and intelligent controllers: a case study. In EMSOFT, pages 30--36, 2007. Google ScholarDigital Library
- M. D. Nguyen, M. Wedler, D. Stoffel, and W. Kunz. Formal hardware/software co-verification by interval property checking with abstraction. In DAC, pages 510--515, 2011. Google ScholarDigital Library
- R. Polig, K. Atasu, L. Chiticariu, C. Hagleitner, H. P. Hofstee, F. R. Reiss, H. Zhu, and E. Sitaridi. Giving text analytics a boost. Micro, 34(4):6--14, 2014.Google Scholar
- R. Polig, K. Atasu, H. Giefers, and L. Chiticariu. Compiling text analytics queries to FPGAs. In FPL, pages 1--6, 2014.Google ScholarCross Ref
- S. Swan. SystemC transaction level models and RTL verification. In DAC, pages 90--92, 2006. Google ScholarDigital Library
- B. Wile. Coherent Accelerator Processor Interface (CAPI) for POWER8 Systems. IBM White Paper, Sep 2014.Google Scholar
- F. Xie and H. Liu. Unified property specification for hardware/software co-verification. In COMPSAC, volume 1, pages 483--490, July 2007. Google ScholarDigital Library
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