Jin Hee Kim
Abstract
In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.
- Victor Aken’Ova. 2005. Bridging the Gap Between Soft and Hard eFPGA Design. Master’s Thesis. University of British Columbia.Google Scholar
- Victor Aken’Ova, Guy Lemieux, and Resve Saleh. 2005. An improved “soft” eFPGA design and implementation strategy. In Proceedings of the 2005 IEEE CICC Conference (CICC’05). 179--182.Google ScholarCross Ref
- Victor Aken’Ova and Resve Saleh. 2006. A “soft++” eFPGA physical design approach with case studies in 180nm and 90nm. In Proceedings of the 2006 ISVLSI Conference (ISVLSI’06). IEEE, Los Alamitos, CA.Google Scholar
- Altera. 2015. Stratix III ALM Logic Structure’s 8-Input Fracturable LUT. Technical Report. Altera Corporation. https://www.altera.com/products/fpga/features/st3-logic-structure.html.Google Scholar
- Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer. Google ScholarCross Ref
- Vaughn Betz and Jonathan Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 1997 FPL Conference (FPL’97). 213--222. Google ScholarCross Ref
- S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic. 2012. Field-Programmable Gate Arrays. Springer International Series in Engineering and Computer Science, Vol. 180. Springer Science 8 Business Media.Google Scholar
- S. Chaudhuri, J.-L. Danger, and S. Guilley. 2007. Efficient modeling and floorplanning of embedded-FPGA fabric. In Proceedings of the 2007 FPL Conference (FPL’07). IEEE, Los Alamitos, CA, 665--669. Google ScholarCross Ref
- S. Chaudhuri, S. Guilley, F. Flament, P. Hoogvorst, and J.-L. Danger. 2008. An 8x8 run-time reconfigurable FPGA embedded in a SoC. In Proceedings of the 2008 DAC Conference (DAC’08). 120--125. Google ScholarDigital Library
- Charles Chiasson and Vaughn Betz. 2013. Should FPGAs abandon the pass-gate? In Proceedings of the 2013 FPL Conference (FPL’13). IEEE, Los Alamitos, CA, 1--8. Google ScholarCross Ref
- W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa. 2015. A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique. IEEE Journal of Solid-State Circuits 50, 1, 68--80. Google ScholarCross Ref
- C. Ebeling, D. Cronquist, and P. Franklin. 1996. RaPiD reconfigurable pipelined datapath. In Field-Programmable Logic Smart Applications, New Paradigms and Compilers. Lecture Notes in Computer Science, Vol. 1142. Springer, 126--135. Google ScholarCross Ref
- E. Fluhr, J. Friedrich, D. M. Dreps, and M. M. Ziegler. 2014. POWER8: A 12-core server-class processor in 22nm SOI with 7.6tb/s off-chip bandwidth. In Proceedings of the 2014 ISSCC Conference (ISSCC’14). IEEE, Los Alamitos, CA, 96--97.Google Scholar
- N. Kafafi, K. Bozman, and S. J. E. Wilton. 2003. architectures and algorithms for synthesizable embedded programmable logic cores. In Proceedings of the 2003 FPGA Conference (FPGA’03). ACM, New York, NY, 3--11. Google ScholarDigital Library
- Jin Hee Kim and Jason H Anderson. 2015. Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. In Proceedings of the 2015 FPL Conference (FPL’15). IEEE, Los Alamitos, CA, 1--8.Google Scholar
- Ian Kuon, Aaron Egier, and Jonathan Rose. 2005. Design, layout and verification of an FPGA using automated tools. In Proceedings of the 2005 FPGA Conference (FPGA’05). ACM, New York, NY, 215--226. Google ScholarDigital Library
- Ian Kuon and Jonathan Rose. 2007. Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 2, 203--215. Google ScholarDigital Library
- Hao Jun Liu. 2014. Archipelago—An Open Source FPGA with Toolflow Support. Master’s Thesis. University of California at Berkeley.Google Scholar
- J. Luu. 2014. Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays. Ph.D. Dissertation. University of Toronto.Google Scholar
- K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. 2013. Titan: Enabling large and complex benchmarks in academic CAD. In Proceedings of the 2013 FPL Conference (FPL’13). IEEE, Los Alamitos, CA. Google ScholarCross Ref
- S. Phillips and S. Hauck. 2002. Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. In Proceedings of the 2002 FPGA Conference (FPGA’02). ACM, Los Alamitos, CA, 165--173. Google ScholarDigital Library
- J. Rose, J. Luu, C. W. Yu, O. Densmore, J. Goeders, A. Somerville, K. B. Kent, P. Jamieson, and J. Anderson. 2012. The VTR project: Architecture and CAD for FPGAs from Verilog to Routing. In Proceedings of the 2012 FPGA Conference (FPGA’12). ACM, New York, NY, 77--86. Google ScholarDigital Library
- S. Wilton, C. H. Ho, B. Quinton, P. H. W. Leong, and W. Luk. 2007. A synthesizable datapath-oriented embedded FPGA fabric. In Proceedings of the 2007 FPGA Conference (FPGA’07). ACM, New York, NY, 33--41. Google ScholarDigital Library
- H. Wong, V. Betz, and J. Rose. 2011. Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture. In Proceedings of the 2011 FPGA Conference (FPGA’11). ACM, New York, NY, 5--14. Google ScholarDigital Library
- S. Yang. 1991. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0. Microelectronics Center of North Carolina.Google Scholar
- Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, and Paolo Ienne. 2016. FPRESSO: Enabling express transistor-level exploration of FPGA architectures. In Proceedings of the 2016 FPGA Conference (FPGA’16). Google ScholarDigital Library
Index Terms
- Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
Recommendations
A Mixed-Grained Reconfigurable Computing Platform for Multiple-Standard Video Decoding (Abstract Only)
FPGA '15: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate ArraysA mixed-grained reconfigurable computing platform targeting multiple-standard video decoding is proposed in this paper. The platform integrates eight coarse-grained Reconfigurable Processing Units (RPUs), each of which consists of 16×16 multi-functional ...
Intel nehalem processor core made FPGA synthesizable
FPGA '10: Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arraysWe present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs. To our knowledge, this is the first time a modern state-...
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder
This paper presents an FPGA-oriented implementation methodology for the MPEG-4 video decoder based on a hardware/software co-design approach. The MPEG-4 decoder is based on MoMuSys optimized reference software combined with new hardware VLSI ...
Comments