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RENO: a high-efficient reconfigurable neuromorphic computing accelerator design

Published:07 June 2015Publication History

ABSTRACT

Neuromorphic computing is recently gaining significant attention as a promising candidate to conquer the well-known von Neumann bottleneck. In this work, we propose RENO -- a efficient reconfigurable neuromorphic computing accelerator. RENO leverages the extremely efficient mixed-signal computation capability of memristor-based crossbar (MBC) arrays to speedup the executions of artificial neural networks (ANNs). The hierarchically arranged MBC arrays can be configured to a variety of ANN topologies through a mixed-signal interconnection network (M-Net). Simulation results on seven ANN applications show that compared to the baseline general-purpose processor, RENO can achieve on average 178.4x (27.06x) performance speedup and 184.2x (25.23x) energy savings in high-efficient multilayer perception (high-accurate auto-associative memory) implementation. Moreover, in the comparison to a pure digital neural processing unit (D-NPU) and a design with MBC arrays co-operating through a digital interconnection network, RENO still achieves the fastest execution time and the lowest energy consumption with similar computation accuracy.

References

  1. "Macsim," http://code.google.com/p/macsim/.Google ScholarGoogle Scholar
  2. "The mnist database," http://yann.lecun.com/exdb/mnist/.Google ScholarGoogle Scholar
  3. "Uci machine learning," http://archive.ics.uci.edu/ml/.Google ScholarGoogle Scholar
  4. F. Alibart et al., "High precision tuning of state for memristive devices by adaptable variation-tolerant algorithm," Nanotechnology, vol. 23, no. 7, 2012.Google ScholarGoogle Scholar
  5. B. Belhadj et al., "Continuous real-world inputs can open up alternative accelerator designs," in ISCA, 2013, pp. 1--12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  6. L. O. Chua, "Memristor-the missing circuit element," Circuit Theory, vol. 18, no. 5, pp. 507--519, 1971.Google ScholarGoogle ScholarCross RefCross Ref
  7. L. Dai and R. Harjani, "Cmos switched-op-amp-based sample-and-hold circuit," in IEEE Transactions on Solid-state circuits, 2000.Google ScholarGoogle Scholar
  8. H. Esmaeilzadeh et al., "Neural acceleration for general-purpose approximate programs," in MICRO, 2012, pp. 449--460. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. J. Gu et al., "Implementation and evaluation of deep neural networks (dnn) on mainstream heterogeneous systems," in APSys, 2014, p. 12. Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. M. Gustavsson, J. J. Wikner, and N. Tan, CMOS data converters for communications, 2000. Google ScholarGoogle ScholarDigital LibraryDigital Library
  11. S. O. Haykin, Neural Networks and Learning Machines. London: Prentice Hall, 2008.Google ScholarGoogle Scholar
  12. M. Hu et al., "Hardware realization of bsb recall function using memristor crossbar arrays," in DAC, 2012, pp. 498--503. Google ScholarGoogle ScholarDigital LibraryDigital Library
  13. N. Jian et al., "A detailed and flexible cycle-accurate network-on-chip simulator," in ISPASS, 2013, pp. 86--96.Google ScholarGoogle Scholar
  14. K.-H. Kim et al., "A functional hybrid memristor crossbar-array/cmos system for data storage and neuromorphic applications," Nano letters, vol. 12, no. 1, pp. 389--395, 2011.Google ScholarGoogle ScholarCross RefCross Ref
  15. S. Li et al., "Mcpat: an integrated power, area, and timing modeling framework for multicore and manycore architectures," in MICRO, 2009, pp. 469--480. Google ScholarGoogle ScholarDigital LibraryDigital Library
  16. B. Liu et al., "Digital assisted noise eliminating training for memristor crossbar based analog neuromorphic computing engine," in DAC, 2013, pp. 1--6. Google ScholarGoogle ScholarDigital LibraryDigital Library
  17. X. Liu et al., "A heterogeneous computing system with memristor-based neuromorphic accelerators," in HPEC, 2014, pp. 1--6.Google ScholarGoogle Scholar
  18. L. Prechelt, "Proben1-a set of neural network benchmark problems and benchmarking rules," University of Karlsruhe, Tech. Rep., 1994.Google ScholarGoogle Scholar
  19. O. Temam, "A defect-tolerant accelerator for emerging high-performance applications," in ISCA, 2012, pp. 356--367. Google ScholarGoogle ScholarDigital LibraryDigital Library

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          cover image ACM Conferences
          DAC '15: Proceedings of the 52nd Annual Design Automation Conference
          June 2015
          1204 pages
          ISBN:9781450335201
          DOI:10.1145/2744769

          Copyright © 2015 ACM

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          Publication History

          • Published: 7 June 2015

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