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In-circuit temporal monitors for runtime verification of reconfigurable designs

Published:07 June 2015Publication History

ABSTRACT

We present designs for in-circuit monitoring of custom hardware designs implemented in reconfigurable hardware. The monitors check hardware designs against temporal logic specifications. Compared to previous work, which uses custom hardware to monitor software, our designs can run at higher speeds and make better use of hardware resources, such as shift registers and embedded memory blocks. We evaluate our monitor circuits on example hardware designs targeting FPGA implementation, showing that they have low overhead in terms of circuit area, and can run at the same speed as the circuits they monitor.

References

  1. Vasudevan, S.: What is assertion-based verification? SIGDA E-News 42(12) (December 2012)Google ScholarGoogle Scholar
  2. Curreri, J., Stitt, G., George, A. D.: High-level synthesis of in-circuit assertions for verification, debugging, and timing analysis. International Journal of Reconfigurable Computing 2011 (2011) Google ScholarGoogle ScholarDigital LibraryDigital Library
  3. Reinbacher, T., Függer, M., Brauer, J.: Real-time runtime verification on chip. In Qadeer, S., Tasiran, S., eds.: Runtime Verification. Volume 7687 of Lecture Notes in Computer Science., Springer Berlin Heidelberg (2013) 110--125Google ScholarGoogle Scholar
  4. Hung, E., Wilton, S.: Incremental trace-buffer insertion for FPGA debug. IEEE Trans. on VLSI 22(4) (April 2014) Google ScholarGoogle ScholarDigital LibraryDigital Library
  5. Hung, E., Todman, T., Luk, W.: Transparent insertion of latency-oblivious logic onto FPGAs. In: Field Programmable Logic and Applications (FPL), 2014 24th International Conference on, IEEE (2014) 1--8Google ScholarGoogle Scholar
  6. Backasch, R., Hochberger, C., Weiss, A., Leucker, M., Lasslop, R.: Runtime verification for multicore SoC with high-quality trace data. ACM Trans. Des. Autom. Electron. Syst. 18(2) (April 2013) 18:1--18:26 Google ScholarGoogle ScholarDigital LibraryDigital Library
  7. Borrione, D., Liu, M., Morin-Allory, K., Ostier, P., Fesquet, L.: On-line assertion-based verification with proven correct monitors. In: Information and Communications Technology, 2005. Enabling Technologies for the New Knowledge Society: ITI 3rd International Conference on. (Dec 2005) 125--143Google ScholarGoogle Scholar
  8. Thati, P., Roşu, G.: Monitoring algorithms for metric temporal logic specifications. Electronic Notes in Theoretical Computer Science 113(0) (2005) 145--162 Proceedings of the Fourth Workshop on Runtime Verification (RV 2004) Fourth Workshop on Runtime Verification 2004. Google ScholarGoogle ScholarDigital LibraryDigital Library
  9. Alur, R., Henzinger, T. A.: Real-time logics: complexity and expressiveness. Information and Computation 104(1) (1993) 35--77 Google ScholarGoogle ScholarDigital LibraryDigital Library
  10. Sheeran, M.: Describing and reasoning about circuits using relations. In McEvoy, K., Tucker, J. V., eds.: Theoretical Foundations of VLSI Design. Cambridge University Press (1990) 263--298 Cambridge Books Online.Google ScholarGoogle ScholarCross RefCross Ref

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  1. In-circuit temporal monitors for runtime verification of reconfigurable designs

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          cover image ACM Conferences
          DAC '15: Proceedings of the 52nd Annual Design Automation Conference
          June 2015
          1204 pages
          ISBN:9781450335201
          DOI:10.1145/2744769

          Copyright © 2015 ACM

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          Publication History

          • Published: 7 June 2015

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