Abstract
“Many-core” systems based on a Network-on-Chip (NoC) architecture offer various opportunities in terms of performance and computing capabilities, but at the same time they pose many challenges for the deployment of real-time systems, which must fulfill specific timing requirements at runtime. It is therefore essential to identify, at design time, the parameters that have an impact on the execution time of the tasks deployed on these systems and the upper bounds on the other key parameters. The focus of this work is to determine an upper bound on the traversal time of a packet when it is transmitted over the NoC infrastructure. Towards this aim, we first identify and explore some limitations in the existing recursive-calculus-based approaches to compute the Worst-Case Traversal Time (WCTT) of a packet. Then, we extend the existing model by integrating the characteristics of the tasks that generate the packets. For this extended model, we propose an algorithm called “Branch and Prune” (BP). Our proposed method provides tighter and safe estimates than the existing recursive-calculus-based approaches. Finally, we introduce a more general approach, namely “Branch, Prune and Collapse” (BPC) which offers a configurable parameter that provides a flexible trade-off between the computational complexity and the tightness of the computed estimate. The recursive-calculus methods and BP present two special cases of BPC when a trade-off parameter is 1 or ∞, respectively. Through simulations, we analyze this trade-off, reason about the implications of certain choices, and also provide some case studies to observe the impact of task parameters on the WCTT estimates.
- L. Benini and G. De Micheli. 2002. Networks on chips: A new soc paradigm. Comput. 35, 1, 70--78. Google ScholarDigital Library
- J.-Y. L. Boudec. and P. Thiran. 2004. Network Calculus—A Theory of Deterministic Queuing Systems for the Internet. Springer.Google Scholar
- W. Dally. 1992. Virtual-channel flow control. IEEE Trans. Parallel Distrib. Syst. 3, 2, 194--205. Google ScholarDigital Library
- W. Dally and C. Seitz. 1986. The torus routing chip. Distrib. Comput. 1, 187--196.Google ScholarCross Ref
- D. Dasari, B. Andersson, V. Nelis, S. M. Petters, A. Easwaran, and J. Lee. 2011. Response time analysis of cots-based multicores considering the contention on the shared memory bus. In Proceedings of the 10th IEEE International Conference on Trust, Security and Privacy in Computing and Communications. 1068--1075. Google ScholarDigital Library
- J. Diemer and R. Ernst. 2010. Back suction: Service guarantees for latency-sensitive on-chip networks. In Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS'10). 155--162. Google ScholarDigital Library
- J. T. Draper and J. Ghosh. 1994. A comprehensive analytical model for wormhole routing in multicomputer systems. J. Parallel Distrib. Comput. 23, 2, 202--214. Google ScholarDigital Library
- T. Ferrandiz, F. Frances, and C. Fraboul. 2009. A method of computation for worst-case delay analysis on spacewire networks. In Proceedings of the IEEE International Symposium on Industrial Embedded Systems (SIES'09). 19--27.Google Scholar
- T. Ferrandiz, F. Frances, and C. Fraboul. 2011. Using network calculus to compute end-to-end delays in spacewire networks. SIGBED Rev. 8, 3, 44--47. Google ScholarDigital Library
- T. Ferrandiz, F. Frances, and C. Fraboul. 2012. A sensitivity analysis of two worst-case delay computation methods for spacewire networks. In Proceedings of the Euromicro Conference on Real-Time Systems. 47--56. Google ScholarDigital Library
- K. Goossens, J. Dielissen, and A. Radulescu. 2005. Aethereal network on chip: Concepts, architectures, and implementations. IEEE Des. Test Comput. 22, 5, 414--421. Google ScholarDigital Library
- J. Hu and R. Marculescu. 2003. Energy-aware mapping for tile-based noc architectures under performance constraints. In Proceedings of the 8th Design Automation Conference. 233--239. Google ScholarDigital Library
- INTEL. 2010. The single-chip-cloud computer. http://www.intel.com/content/dam/www/public/us/en/documents/technology-briefs/intel-labs-singlechip-cloud-article.pdf.Google Scholar
- K. Knauber and B. Chen. 1999. Supporting preemption in wormhole networks. In Proceedings of the 23rd Annual International Computer Software and Applications Conference (COMPSAC'99). 232--238. Google ScholarDigital Library
- S. Lee. 2003. Real-time wormhole channels. J. Parallel Distrib. Comput. 63, 299--311. Google ScholarDigital Library
- Z. Lu, A. Jantsch, and I. Sander. 2005. Feasibility analysis of messages for on-chip networks using wormhole routing. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'05). 960--964. Google ScholarDigital Library
- C. Paukovits and H. Kopetz. 2008. Concepts of switching in the time-triggered network-on-chip. In Proceedings of the 14th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications. 120--129. Google ScholarDigital Library
- R. Pellizzoni, A. Schranzhofer, J.-J. Chen, M. Caccamo, and L. Thiele. 2010. Worst case delay analysis for memory interference in multicore systems. In Proceedings of the Conference on Design, Automation and Test in Europe. 741--746. Google ScholarDigital Library
- Y. Qian, Z. Lu, and W. Dou. 2010. Analysis of worst-case delay bounds for on-chip packet-switching networks. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst. 29, 802--815. Google ScholarDigital Library
- D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, and H. Sarbazi-Azad. 2009. A method for calculating hard qos guarantees for networks-on-chip. In Proceedings of the International Conference on Computer-Aided Design. 579--586. Google ScholarDigital Library
- E. Salminen, A. Kulmala, and T. Hamalainen. 2008. Survey of network-on-chip proposals. www.ocpip.org.Google Scholar
- S. Schliecker, M. Negrean, and R. Ernst. 2010. Bounding the shared resource load for the performance analysis of multiprocessor systems. In Proceedings of the Conference on Design, Automation and Test in Europe. 759--764. Google ScholarDigital Library
- Z. Shi and A. Burns. 2008. Real-time communication analysis for on-chip networks with wormhole switching. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip. 161--170. Google ScholarDigital Library
- Tilera. 2011. Tile processor: User architecture manual. www.tilera.com/scm/docs/UG101-User-Architecture-Reference.pdf.Google Scholar
- D. Wentzlaff, P. Griffin, H. Hoffmann, L. Bao, B. Edwards, C. Ramey, M. Mattina, C.-C. Miao, J. F. Brown III., and A. Agarwal. 2007. On-chip interconnection architecture of the tile processor. IEEE Micro 27, 5, 15--31. Google ScholarDigital Library
Index Terms
- NoC contention analysis using a branch-and-prune algorithm
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