Xin Zhao
ABSTRACT
This paper focuses on low-power clock network design for 3D ICs, where through-silicon vias (TSVs) form a regular 2-dimensional array. This TSV array style is shown to be more manufacturable and practical than layouts with TSVs located at irregular spots. However, due to limited TSV resources in TSV arrays, TSV utilization in a 3D clock network significantly affects the final clock power. A straightforward extension on existing works for TSV arrays cannot guarantee power efficiency. Therefore, we develop a decision-tree-based clock synthesis (DTCS) method to generate low-power and reliable clock networks by efficiently exploring the entire solution space for the best TSV array utilization. Our DTCS method has been applied for both gate-level chip-scale 3D clock designs and block-level global clock designs. Experimental results show that our algorithm effectively finds close-to-optimal solutions for power efficiency with skew minimization in short runtime. Our DTCS method achieves up to 13.5% average power reduction with more than 50% fewer TSVs compared with the straightforward extension on the existing algorithm.
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Digital Library
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Index Terms
- TSV array utilization in low-power 3D clock network design
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