ABSTRACT
Due to the large geometry of through-silicon-vias (TSVs) and their connections to the power grid, significant current crowding can occur in 3D ICs. Prior works model TSVs and power wire segments as single resistors, which cannot capture the detailed current distribution and may miss trouble spots associated with current crowding. This paper studies DC current crowding and its impact on 3D power integrity. First, we explore the current density distribution within a TSV and its power wire connections. Second, we build and validate effective TSV models for current density distributions. Finally, these models are integrated with global power wires for detailed chip-scale power grid analysis.
- J. Abella and X. Vera. Electromigration for Microarchitects. ACM Comput. Surv., 42(2):9:1--9:18, March 2010. Google ScholarDigital Library
- M. B. Healy and S. K. Lim. Distributed TSV Topology for 3-D Power-Supply Networks. IEEE Trans. on VLSI Systems, PP(99):1--14, October 2011.Google Scholar
- C. Huyghebaert, J. Van Olmen, Y. Civale, A. Phommahaxay, A. Jourdain, S. Sood, S. Farrens, and P. Soussan. Cu to Cu interconnect using 3D-TSV and wafer to wafer thermocompression bonding. In International Interconnect Technology Conference, pages 1--3, 2010.Google ScholarCross Ref
- M. Jung, J. Mitra, D. Pan, and S. K. Lim. TSV Stress-aware Full-Chip Mechanical Reliability Analysis and Optimization for 3D IC. In Proc. ACM Design Automation Conf., pages 188--193, 2011. Google ScholarDigital Library
- S. Karmalkar, P. Mohan, H. Nair, and R. Yeluri. Compact Models of Spreading Resistances for ElectricalThermal Design of Devices and ICs. IEEE Trans. on Electron Devices, 54(7):1734--1743, July 2007.Google ScholarCross Ref
- N. Khan, S. Alam, and S. Hassoun. Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies. IEEE Trans. on VLSI Systems, 19(4):647--658, April 2011. Google ScholarDigital Library
- S. R. Nassif and J. N. Kozhayz. Fast Power Grid Simulation. In Proc. ACM Design Automation Conf., pages 156--161, 2000. Google ScholarDigital Library
- Y. C. Tan, C. M. Tan, X. W. Zhang, T. C. Chai, and D. Q. Yu. Electromigration performance of Through Silicon Via (TSV), A modeling approach. Microelectronics Reliability, 50(9--11):1336--1340, Sept.-Nov. 2010.Google Scholar
Index Terms
- Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs
Recommendations
Through-silicon-via-aware delay and power prediction model for buffered interconnects in 3D ICs
SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect predictionIn this paper, we present a delay and power prediction model for buffered interconnects used in 3D ICs. The key idea is to model the impact of RC parasitics of Through-Silicon Vias (TSVs) used in 3D interconnects on delay and power consumption. Due to ...
Effect of TSV fabrication technology on power distribution in 3D ICs
GLSVLSI '13: Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSIThe design implications of two distinct through silicon via (TSV) fabrication methods (via-first and via-last) have been investigated for power delivery in a 3D system. Different geometry, connectivity, and filling materials have been considered to ...
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs
SLIP '09: Proceedings of the 11th international workshop on System level interconnect predictionIndividual dies in 3D integrated circuits are connected using through-silicon-vias (TSVs). TSVs not only increase manufacturing cost, but also incur silicon area, delay, and power overhead. However, the effects of TSV overheads have not been studied ...
Comments