ABSTRACT
In this paper, we present an approved linear-time algorithm for statistical leakage analysis in the present of any spatial correlation condition (strong or weak). The new algorithm adopts a new set of uncorrelated variables over virtual grids to represent the original physical random variables and the grid size (thus of number of new random variables) is determined by the spatial correlation length. In this way, each physical variable is always represented by virtual variables locally. We prove that the number of neighboring virtual grids for each grid is not related to condition of spatial correlation, which leads to linear time complexity in terms of number of gates. We compute the gate leakage by the orthogonal polynomials based collocation method. The total leakage of a whole chip can be computed by simply summing up the coefficients of corresponding orthogonal polynomials for each grid. Furthermore, look-up table can be created to cache statistical information for each type of gates in library instead of calculating leakage for every single gate on chip. As a result, we end up with O(N) time complexity, where N is the number of grids on chip. The proposed method has no restrictions on static leakage models, types of statistical distributions for leakage currents. Experimental results show that the proposed method is about 1000X faster than the recently proposed grid-based method [2] with similar accuracy and many orders of magnitude times over the Monte Carlo method.
- International technology roadmap for semiconductors(ITRS), 2008. http://public.itrs.net.Google Scholar
- H. Chang and S. S. Sapatnekar. Full-chip analysis of leakage power under process variations, including spatial correlations. In Proc. IEEE Design Automation Conference (DAC), pp. 523--528, 2005. Google ScholarDigital Library
- R. Chen, L. Zhang, V. Zolotov, C. Visweswariah, and J. Xiong. Static timing: back to our roots. In Proc. Asia South Pacific Design Automation Conf.(ASPDAC), pp. 310--315, Jan. 2008. Google ScholarDigital Library
- R. G. Ghanem and P. D. Spanos. Stochastic Finite Elements: A Spectral Approach. Dover Publications, 2003. Google ScholarDigital Library
- K. R. Heloue, N. Azizi, and F. N. Najm. Modeling and estimation of full-chip leakage current considering within-die correlation. In Proc. IEEE Design Automation Conference (DAC), pp. 93--98, 2007. Google ScholarDigital Library
- X. Li, J. Le, and L. T. Pileggi. Projection-based statistical analysis of full--chip leakage power with non--log--normal distributions. In Proc. IEEE Design Automation Conference (DAC), pp. 103--108, July 2006. Google ScholarDigital Library
- S. Narendra, V. De, S. Borkar, D. A. Antoniadis, and A. P. Chandrakasan. Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18um CMOS. IEEE J. Solid-State Circuits, 39(2), 2004.Google Scholar
- S. Nassif. Delay variability: sources, impact and trends. In Proc. IEEE Int. Solid-State Circuits Conf., pp. 368--369, San Francisco, CA, Feb 2000.Google Scholar
- E. Novak and K. Ritter. Simple cubature formulas with high polynomial exactness. Constructive Approximation, 15(4):449--522, Dec 1999.Google ScholarCross Ref
- D. O. Ouma, D. S. Boning, J. E. Chung, W. G. Easter, V. Saxena, S. Misra, and A. Crevasse. Characterization and modeling of oxide chemical-mechanical polishing using planarization length and pattern density concepts. IEEE Trans. on Semiconductor Manufacturing, 15(2):232--244, May 2002.Google ScholarCross Ref
- Predictive technology model. http://www.eas.asu.edu/~ptm/.Google Scholar
- R. Rao, A. Srivastava, D. Blaauw, and D. Sylvester. Statistical analysis of subthreshold leakage current for VLSI circuits. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 12(2):131--139, Feb 2004. Google ScholarDigital Library
- R. Shen, N. Mi, S. X.-D. Tan, Y. Cai, and X. Hong. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method. In Proc. Asia South Pacific Design Automation Conf. (ASPDAC), pp. 161--166, Jan. 2009. Google ScholarDigital Library
- R. Teodorescu, B. Greskamp, J. Nakano, S. R. Sarangi, A. Tiwari, and J. Torrellas. A model of parameter variation and resulting timing errors for microarchitects. In Workshop on Architectural Support for Gigascale Integration (ASGI), Jun 2007.Google Scholar
- J. M. Wang, B. Srinivas, D. Ma, C. C.-P. Chen, and J. Li. System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS). In Proc. Int. Conf. on Computer Aided Design (ICCAD), pp. 727--734, Nov. 2005. Google ScholarDigital Library
- J. Xiong, V. Zolotov, and L. He. Robust extraction of spatial correlation. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 26(4), 2007. Google ScholarDigital Library
- Z. Ye and Z. Yu. An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis. In Proc. Int. Conf. on Computer Aided Design (ICCAD), pp. 295--301, Nov. 2009. Google ScholarDigital Library
Index Terms
- A linear statistical analysis for full-chip leakage power with spatial correlation
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