Linwei Niu
ABSTRACT
While the dynamic voltage scaling (DVS) techniques are efficient in reducing the dynamic energy consumption for the processor, varying voltage alone becomes less effective for the overall power reduction as the leakage power is growing rapidly, i.e., five times per technical generation as predicted. In this paper, we study the problem of reducing both the static and dynamic power consumption at the same time for the hard real-time system scheduled by the earliest deadline first (EDF) strategy. To balance the dynamic and leakage energy consumption, higher-than-necessary processor speeds may be required when executing real-time tasks, which can result in a large number of idle intervals. To effectively reduce the energy consumption during these idle intervals, we propose a technique that can effectively merge these scattered intervals into larger ones without causing any deadline miss. Simulation studies demonstrate the effectiveness of our approach. Specifically, our experiments show that the proposed technique can lead up to more than 80% idle energy savings than that by the previous ones.
- F. Assaderaghi, D. Sinitsky, S. A. Parke, J. Bokor, P. Ko, and C. Hu. Dynamic threshold-voltage mosfet (dtmos) for ultra-low voltage vlsi. IEEE Trans. on Elec. Dev., 44(3):414--422, Mar 1997.Google Scholar
Cross Ref
- H. Aydin, R. Melhem, D. Mosse, and P. Alvarez. Dynamic and aggressive scheduling techniques for power aware real-time systems. RTSS, 2001. Google ScholarDigital Library
- B. H. Calhoun, F. A. Honore, and A. Chandrakasan. Design methodology for fine-grained leakage control in mtcmos. ISLPED, pages 104--109, 2003. Google ScholarDigital Library
- A. P. Chandrakasan, S. Sheng, and R. W. Brodersen. Low-power cmos digital design. IEEE Journal of Solid-State Circuits, 27(4):473--484, April 1992.Google ScholarCross Ref
- S. Duarte, Y. Tsai, N. Vijaykrishnan, and M. Irwin. Evaluating run-time techniques for leakage power reduction. VLSID'02, 2002. Google ScholarDigital Library
- J. Halter and F. Najm. A gate-level leakage power reduction method for ultra low power cmos circuits. CICC, pages 475--478, 1997.Google ScholarCross Ref
- Intel. PXA250 and PXA210 Applications Processors Design Guide. Intel, 2002.Google Scholar
- S. Irani, S. Shukla, and R. Gupta. Algorithms for power savings. ISDA, 2003. Google ScholarDigital Library
- T. Ishihara and H. Yasuura. Voltage scheduling problem for dynamically variable voltage processors. ISLPED, pages 197--202, August 1998. Google ScholarDigital Library
- ITRS. International Technology Roadmap for Semiconductors. International SEMATECH, Austin, TX., http://public.itrs.net/.Google Scholar
- R. Jejurikar, C. Pereira, and R. Gupta. Leakage aware dynamic voltage scaling for real-time embedded systems. DAC, pages 275 -- 280, 2004. Google ScholarDigital Library
- M. Johnson, D. Somasekhar, and K. Roy. Leakage control with efficient use of transistor stacks in single threshold cmos. DAC, pages 442--445, 1999. Google ScholarDigital Library
- Y. Lee, K. Reddy, and C. Krishna. Scheduling techniques for reducing leakage power in hard real-time systems. ECRTS, 2003.Google Scholar
- C. L. Liu and J. W. Layland. Scheduling algorithms for multiprogramming in a hard real-time environment. Journal of the ACM, 17(2):46--61, 1973. Google ScholarDigital Library
- S. Martin, K. Flautner, T. Mudge, and D. Blaauw. Combined dynamic voltage scaling and adaptive body biasing for lower power microporcessor under dynamic workloads. ICCAD, 2002. Google ScholarDigital Library
- B. Mochocki, X. Hu, and G. Quan. A realistic variable voltage scheduling model for real-time applications. ICCAD, 2002. Google ScholarDigital Library
- C. Neau and K. Roy. Optimal body bias selection for leakage improvement and process compensation over different technology generations. ISLPED, pages 116--121, 2003. Google ScholarDigital Library
- P. Pillai and K. G. Shin. Real-time dynamic voltage scaling for low-power embedded operating systems. In SOSP, 2001. Google ScholarDigital Library
- L. Yan, J. Luo, and N. K. Jha. Combined dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems. ICCAD, 2003. Google ScholarDigital Library
- F. Yao, A. Demers, and S. Shenker. A scheduling model for reduced cpu energy. FOCS, pages 374--382, 1995. Google ScholarDigital Library
Index Terms
- Reducing both dynamic and leakage energy consumption for hard real-time systems
Recommendations
Dynamic voltage scaling for systemwide energy minimization in real-time embedded systems
ISLPED '04: Proceedings of the 2004 international symposium on Low power electronics and designTraditionally, dynamic voltage scaling (DVS) techniques have focused on minimizing the processor energy consumption as opposed to the entire system energy consumption. The slowdown resulting from DVS can increase the energy consumption of components ...
Energy aware kernel for hard real-time systems
CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systemsEmbedded systems often have severe power and energy constraints. Dynamic voltage scaling (DVS) is a mechanism by which energy consumption may be reduced. In this paper, we implement a dynamic voltage scaling based scheduler in the eCos operating system ...
Joint dynamic voltage scaling and adaptive body biasing for heterogeneous distributed real-time embedded systems
While dynamic power consumption has traditionally been the primary source of power consumption, leakage power is becoming an increasingly important concern as technology feature size continues to shrink. Previous system-level approaches focus on ...
Comments