Terry Ching-Hsiang Hsu
ABSTRACT
Non-volatile memory technologies, such as memristor and phase-change memory, will allow programs to persist data with regular memory instructions. Liberated from the overhead to serialize and deserialize data to storage devices, programs can aim for high performance and still be crash fault-tolerant. Unfortunately, to leverage non-volatile memory, existing systems require hardware changes or extensive program modifications.
We present NVthreads, a programming model and runtime that adds persistence to existing multi-threaded C/C++ programs. NVthreads is a drop-in replacement for the pthreads library and requires only tens of lines of program changes to leverage non-volatile memory. NVthreads infers consistent states via synchronization points, uses the process memory to buffer uncommitted changes, and logs writes to ensure a program's data is recoverable even after a crash. NVthreads' page level mechanisms result in good performance: applications that use NVthreads can be more than 2× faster than state-of-the-art systems that favor fine-grained tracking of writes. After a failure, iterative applications that use NVthreads gain speedups by resuming execution.
- Stanford network analysis package. http://snap.stanford.edu/snap, 2009.Google Scholar
- Tokyo Cabinet: a modern implementation of DBM. http://fallabs.com/tokyocabinet/, 2010.Google Scholar
- Intel and Micron produce breakthrough memory technology. http://newsroom.intel.com/docs/DOC-6713, 2015.Google Scholar
- SanDisk and HP launch partnership to create memory-driven computing solutions. http://www8.hp.com/us/en/hpnews/press-release.html?id=2099577, 2015.Google Scholar
- Intel 64 and ia-32 architectures optimization reference manual. http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf, 2016.Google Scholar
- J. Ansel, K. Arya, and G. Cooperman. DMTCP: Transparent checkpointing for cluster computations and the desktop. In 23rd IEEE International Parallel and Distributed Processing Symposium, Rome, Italy, May 2009. Google ScholarDigital Library
- A. Aviram, S.-C. Weng, S. Hu, and B. Ford. Efficient system-enforced deterministic parallelism. In Proceedings of the 9th USENIX Conference on Operating Systems Design and Implementation, OSDI'10, pages 1--16, Berkeley, CA, USA, 2010. USENIX Association.Google ScholarDigital Library
- L. Backstrom, D. Huttenlocher, J. Kleinberg, and X. Lan. Group formation in large social networks: Membership, growth, and evolution. In Proceedings of the 12th ACM SIGKDD International Conference on Knowledge Discovery and Data Mining, KDD '06, pages 44--54, New York, NY, USA, 2006. ACM. Google ScholarDigital Library
- K. Bailey, L. Ceze, S. D. Gribble, and H. M. Levy. Operating system implications of fast, cheap, non-volatile memory. In Proceedings of the 13th USENIX Conference on Hot Topics in Operating Systems, HotOS'13, pages 2--2, Berkeley, CA, USA, 2011. USENIX Association.Google ScholarDigital Library
- A. Basu, J. Gandhi, J. Chang, M. D. Hill, and M. M. Swift. Efficient virtual memory for big memory servers. In Proceedings of the 40th Annual International Symposium on Computer Architecture, ISCA '13, pages 237--248, New York, NY, USA, 2013. ACM. Google ScholarDigital Library
- C. Bienia and K. Li. PARSEC 2.0: A new benchmark suite for chip-multiprocessors. In Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, June 2009.Google Scholar
- S. Brin and L. Page. The anatomy of a large-scale hypertextual Web search engine. In WWW7, 1998. Google ScholarDigital Library
- D. R. Butenhof. Programming with POSIX Threads. Addison-Wesley Longman Publishing Co., Inc., Boston, MA, USA, 1997.Google ScholarDigital Library
- D. R. Chakrabarti, H.-J. Boehm, and K. Bhandari. Atlas: Leveraging locks for non-volatile memory consistency. In Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages & Applications, OOPSLA '14, pages 433--152, New York, NY, USA, 2014. ACM. Google ScholarDigital Library
- J. Coburn, T. Bunker, M. Schwarz, R. Gupta, and S. Swanson. From aries to mars: Transaction support for next-generation, solid-state drives. In Proceedings of the Twenty-Fourth ACM Symposium on Operating Systems Principles, SOSP '13, pages 197--212, New York, NY, USA, 2013. ACM. Google ScholarDigital Library
- J. Coburn, A. M. Caulfield, A. Akel, L. M. Grupp, R. K. Gupta, R. Jhala, and S. Swanson. Nv-heaps: Making persistent objects fast and safe with next-generation, non-volatile memories. SIGPLAN Not., 46(3):105--118, Mar. 2011. Google ScholarDigital Library
- J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Coetzee. Better i/o through byte-addressable, persistent memory. In Proceedings of the ACM SIGOPS 22Nd Symposium on Operating Systems Principles, SOSP '09, pages 133--146, New York, NY, USA, 2009. ACM.Google ScholarDigital Library
- B. Dieny, R. Sousa, G. Prenat, and U. Ebels. Spin-dependent phenomena and their implementation in spintronic devices. In International Symposium on VLSI Technology, Systems and Applications, VLSI '08, pages 70--71. IEEE, 2008. Google ScholarCross Ref
- S. R. Dulloor, S. Kumar, A. Keshavamurthy, P. Lantz, D. Reddy, R. Sankaran, and J. Jackson. System software for persistent memory. In Proceedings of the Ninth European Conference on Computer Systems, EuroSys '14, pages 15:1--15:15, New York, NY, USA, 2014. ACM. Google ScholarDigital Library
- E. Giles, K. Doshi, and P. J. Varman. Softwrap: A lightweight framework for transactional support of storage class memory. In MSST, pages 1--14. IEEE Computer Society, 2015. Google ScholarCross Ref
- J. Izraelevitz, T. Kelly, and A. Kolli. Failure-atomic persistent memory updates via justdo logging. In Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS '16, pages 427--142, New York, NY, USA, 2016. ACM. Google ScholarDigital Library
- O. Laadan and J. Nieh. Transparent checkpoint-restart of multiple processes on commodity operating systems. In 2007 USENIX Annual Technical Conference on Proceedings of the USENIX Annual Technical Conference, ATC'07, pages 25:1--25:14, Berkeley, CA, USA, 2007. USENIX Association.Google Scholar
- B. C. Lee, E. Ipek, O. Mutlu, and D. Burger. Architecting phase change memory as a scalable dram alternative. In Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA '09, pages 2--13, New York, NY, USA, 2009. ACM. Google ScholarDigital Library
- T. Liu, C. Curtsinger, and E. D. Berger. Dthreads: Efficient deterministic multithreading. In Proceedings of the Twenty-Third ACM Symposium on Operating Systems Principles, SOSP '11, pages 327--336, New York, NY, USA, 2011. ACM. Google ScholarDigital Library
- D. E. Lowell and P. M. Chen. Free transactions with rio vista. In Proceedings of the Sixteenth ACM Symposium on Operating Systems Principles, SOSP '97, pages 92--101, New York, NY, USA, 1997. ACM. Google ScholarDigital Library
- C. Mohan, D. Haderle, B. Lindsay, H. Pirahesh, and P. Schwarz. Aries: A transaction recovery method supporting fine-granularity locking and partial rollbacks using write-ahead logging. ACM Trans. Database Syst., 17(1):94--162, Mar. 1992. Google ScholarDigital Library
- D. Narayanan and O. Hodson. Whole-system persistence. In Proceedings of the Seventeenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVII, pages 401--410, New York, NY, USA, 2012. ACM. Google ScholarDigital Library
- J. S. Plank, M. Beck, G. Kingsley, and K. Li. Libckpt: Transparent checkpointing under unix. In Proceedings of the USENIX 1995 Technical Conference Proceedings, TCON'95, pages 18--18, Berkeley, CA, USA, 1995. USENIX Association.Google ScholarDigital Library
- C. Ranger, R. Raghuraman, A. Penmetsa, G. Bradski, and C. Kozyrakis. Evaluating mapreduce for multi-core and multiprocessor systems. In Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture, HPCA '07, pages 13--24, Washington, DC, USA, 2007. IEEE Computer Society. Google ScholarDigital Library
- M. Satyanarayanan, H. H. Mashburn, P. Kumar, D. C. Steere, and J. J. Kistler. Lightweight recoverable virtual memory. ACM Trans. Comput. Syst., 12(1):33--57, Feb. 1994. Google ScholarDigital Library
- R. Sears and E. Brewer. Stasis: Flexible transactional storage. In Proceedings of the 7th Symposium on Operating Systems Design and Implementation, OSDI '06, pages 29--44, Berkeley, CA, USA, 2006. USENIX Association.Google ScholarDigital Library
- V. Singhal, S. V. Kakkad, and P. R. Wilson. Texas: Good, fast, cheap persistence for c++. In Addendum to the Proceedings on Object-oriented Programming Systems, Languages, and Applications (Addendum), OOPSLA '92, pages 145--147, New York, NY, USA, 1992. ACM.Google ScholarDigital Library
- D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams. The missing memristor found. Nature, 453(7191):80--83, May 2008. Google ScholarCross Ref
- H. Volos, A. J. Tack, and M. M. Swift. Mnemosyne: Lightweight persistent memory. In Proceedings of the Sixteenth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS XVI, pages 91--104, New York, NY, USA, 2011. ACM.Google ScholarDigital Library
- A. Welc, A. L. Hosking, and S. Jagannathan. Transparently reconciling transactions with locking for java synchronization. In Proceedings of the 20th European Conference on Object-Oriented Programming, ECOOP'06, pages 148--173, Berlin, Heidelberg, 2006. Springer-Verlag. Google ScholarDigital Library
- S. J. White and D. J. DeWitt. Quickstore: A high performance mapped object store. The VLDB Journal, 4(4):629--673, Oct. 1995. Google ScholarDigital Library
- Y. Zhang and S. Swanson. A study of application performance with non-volatile main memory. In IEEE 31st Symposium on Mass Storage Systems and Technologies, MSST 2015, Santa Clara, CA, USA, May 30-June 5, 2015, pages 1--10, 2015. Google ScholarCross Ref
Recommendations
WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory
This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—...
A Novel Memory Block Management Scheme for PCM Using WOM-Code
HPCC-CSS-ICESS '15: Proceedings of the 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security, and 2015 IEEE 12th International Conf on Embedded Software and SystemsPhase Change Memory (PCM) is a promising DRAM replacement in embedded systems due to its attractive characteristics including low static power consumption and high density. However, long write latency is one of the major drawbacks in current PCM ...
Mellow writes: extending lifetime in resistive memories through selective slow write backs
ISCA'16Emerging resistive memory technologies, such as PCRAM and ReRAM, have been proposed as promising replacements for DRAM-based main memory, due to their better scalability, low standby power, and non-volatility. However, limited write endurance is a major ...
Comments