Extraction Method for Substrate-Related Components of Vertical Junctionless Silicon Nanowire Field-Effect Transistors and Its Verification on Radio Frequency Characteristics

In this paper, we propose a radio-frequency (RF) model and parameter extraction method for vertical junctionless silicon nanowire (VJL SNW) field-effect transistors (FETs) using three-dimensional (3D) device simulation. We introduce the substrate-related components such as the substrate resistance (R_sub) and drain-to-substrate capacitance (C_sub), and evaluate the RF performance such as f_t, f_max, gate input capacitance, and transport time delay. A quasi-static (QS) RF model has been used in simulation program with integrated circuit emphasis (SPICE) circuit simulator to simulate VJL SNW FETs with RF parameters extracted from 3D device simulated Y-parameters. We confirmed the validity of our RF model by the well-matched results between HSPICE and 3D device simulation in terms of the Y-parameters and the S₂₂-parameter up to 100 GHz.