Application of Thermal Plasma Jet Irradiation to Crystallization and Gate Insulator Improvement for High-Performance Thin-Film Transistor Fabrication

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Published 22 March 2011 Copyright (c) 2011 The Japan Society of Applied Physics
, , Citation Seiichiro Higashi et al 2011 Jpn. J. Appl. Phys. 50 03CB10 DOI 10.1143/JJAP.50.03CB10

1347-4065/50/3S/03CB10

Abstract

Large grains with a maximum length of ∼60 µm were grown by high speed scanning (∼4000 mm/s) of a molten region in amorphous silicon (a-Si) films formed by micro-thermal-plasma-jet (µ-TPJ) irradiation. By reducing the TPJ nozzle diameter and increasing the spacing between anode and cathode, the power density transferred to a-Si film surface increased to as high as 53 kW/cm2, which enabled melting and lateral solidification in the microsecond time domain. The a-Si transformed to crystalline through solid-phase crystallization, followed by melting and recrystallization induced by the movement of the molten region with the maximum size of ∼483 µm in width and ∼990 µm in length. The laterally crystallized Si films show anisotropic large grains and a high crystalline volume fraction of ∼100% and preferential surface orientation of (111) plane. Thin-film transistors (TFTs) fabricated by solid-phase-crystallized microcrystalline Si (µc-Si) show a small field effect mobility (µFE) of ∼2 cm2 V-1 s-1 with small variation less than 1%, while the high-speed lateral-crystallization (HSLC) Si film shows a very high µFE of 350 cm2 V-1 s-1. We improved the bulk bond network of the low-temperature-deposited gate SiO2 films by TPJ-induced millisecond annealing. By combining TPJ annealing and postmetallization annealing (PMA), a high-quality SiO2/Si interface with a density of interface states (Dit) of 3.0 ×1010 cm-2 eV-1 is obtained. In addition, we found that the improvement in the bulk bond network of SiO2 is quite effective to improve the stress immunity of µc-Si TFTs. TFTs fabricated with TPJ-annealed gate SiO2 films show much smaller on-current degradation and threshold voltage shift after DC bias stress compared with untreated TFTs. Not only the threshold voltage (Vth) shift under high-gate-field stress condition, but also on-current degradation under drain avalanche hot carrier (DAHC) generation condition are markedly suppressed. This improvement is attributed to the reduction of Si–OH bonds and relaxation of the bulk chemical bond network of SiO2 induced by TPJ annealing.

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10.1143/JJAP.50.03CB10