Low-Temperature Behaviors of Phonon-Limited Electron Mobility of Sub-10-nm-Thick Silicon-on-Insulator Metal–Oxide–Semiconductor Field-Effect Transistor with (001) and (111) Si Surface Channels

In this study we simulate the impact of silicon layer thickness and temperature on the phonon-limited electron mobility of the inversion layer for ultrathin-body (111) and (001) surface silicon-on-insulator (SOI) layers in single-gate (SG) and double-gate (DG) SOI metal–oxide–semiconductor field-effect transistors (MOSFETs); one-dimensional self-consistent calculations and relaxation time approximations are performed. For a sub-10-nm-thick SOI layer, it is demonstrated that intra-subband phonon scattering at the lowest subband in the inversion layer on the (111) Si surface of the DG SOI MOSFET is strongly suppressed in a medium-to-high effective field (E_eff) at a low temperature. On the other hand, it is revealed that the contribution of inter-subband phonon scattering in the inversion layer on the (001) Si surface of the DG SOI MOSFET is very large in a medium-to-high E_eff regardless of temperature. Simulation results suggest that the phonon-limited electron mobility on the (111) Si surface of the DG MOSFET will be highly advantageous for future high-performance low-temperature device applications including space applications.