Interface-state passivation during dc biased postmetallization annealing at ∼350 °C was studied in very thin oxide (∼31 Å) metal–tunnel-oxide–silicon structures. The gate metal was aluminum and the substrate was 〈111〉 oriented and of p type. Capacitance-voltage and tunnel-current–voltage measurements were used after the anneals to monitor the passivation of interface states. It was found that the passivation process of the initially present interface states is directly dependent on the surface potential but not on the average oxide electric field or the tunnel current. A negative gate voltage increases the passivation rate, whereas a positive gate voltage decreases it as compared to unbiased annealing. The interface states bear significant resemblances to ${\mathit{P}}_{\mathit{b}}$ centers, which are dangling bonds on trivalently bonded Si atoms at the interface. The present observations are found to agree well with the theoretical calculations by Edwards [Phys. Rev. B 44, 1832 (1991)] on the surface-potential dependence of the passivation of ${\mathit{P}}_{\mathit{b}}$ centers by molecular hydrogen. Furthermore, we report on the impact of biased annealing on the tunnel current and the flatband voltage and also on the behavior of electrically stressed devices during biased annealing. The beneficial effect of a negatively biased annealing makes it possible to find an optimum time and voltage, roughly 1000 s at a gate voltage of -1.2 V in our case, for simultaneously minimizing the dc tunnel current, flatband voltage shifts, and the density of fast interface states in these diodes. None of the passivation events was found to be promoted by annealing in a 10% ${\mathrm{H}}_2$/Ar ambient compared to annealing in an ${\mathrm{N}}_2$ ambient.

• Received 6 May 1994

DOI:https://doi.org/10.1103/PhysRevB.50.11666