Multifunctional Spin Logic Operations in Graphene Spin Circuits

Open Access

Multifunctional Spin Logic Operations in Graphene Spin Circuits

Dmitrii Khokhriakov, Shehrin Sayed, Anamul Md. Hoque, Bogdan Karpiak, Bing Zhao, Supriyo Datta, and Saroj P. Dash

Phys. Rev. Applied 18, 064063 – Published 21 December 2022

Abstract

Spin-based computing, combining logic and nonvolatile magnetic memory, is promising for emerging information technologies. However, the realization of a universal spin logic operation, representing a reconfigurable building block with all-electrical spin-current communication, has so far remained challenging. Here, we experimentally demonstrate reprogrammable all-electrical multifunctional spin logic operations in a nanoelectronic device architecture, utilizing graphene buses for spin communication and mixing and nanomagnets for writing and reading information at room temperature. This device realizes a multistate spin-majority logic operation, which is reconfigured to achieve (n)and, (n)or, and xnor Boolean operations, depending on the magnetization of inputs. The results are in good agreement with the predictions from a spin-circuit model, providing an experimental demonstration of a spin-based logic unit that takes advantage of the vector nature of spin, as opposed to conventional scalar charge-based devices. These spin logic operations in large-area graphene are fully compatible with industrial fabrication processes and represent a promising platform for scalable all-electric spin-based logic-in-memory computing architecture.

Received 12 August 2022
Revised 12 October 2022
Accepted 16 November 2022

DOI:https://doi.org/10.1103/PhysRevApplied.18.064063

Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation, and DOI. Funded by Bibsam.

Published by the American Physical Society

Physics Subject Headings (PhySH)

Magnetotransport Spin current

Devices for digital logic, storage & processing Graphene Nanotechnology

Condensed Matter, Materials & Applied Physics

Authors & Affiliations

Dmitrii Khokhriakov ¹, Shehrin Sayed^2,3, Anamul Md. Hoque ¹, Bogdan Karpiak ¹, Bing Zhao ¹, Supriyo Datta⁴, and Saroj P. Dash ^1,5,*

¹Department of Microtechnology and Nanoscience, Chalmers University of Technology, SE-41296, Göteborg, Sweden
²Department of Electrical Engineering and Computer Sciences, University of California-Berkeley, Berkeley, California 94720, USA
³Materials Science Division, Lawrence Berkeley National Laboratory, Berkeley, California 94720, USA
⁴Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA
⁵Graphene Center, Chalmers University of Technology, SE-41296, Göteborg, Sweden

^*saroj.dash@chalmers.se

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Issue

Vol. 18, Iss. 6 — December 2022

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Images

Figure 1
Spin-majority logic device in a graphene-based spin-integrated circuit. (a) Schematic of a spin-majority logic device with a three-input fan-in circuit, where ferromagnetic contacts are used for writing and reading spin information, and the graphene channel is used for information communication via pure spin currents. (b) Colored SEM image of the spin-majority logic device. Device consists of a three-input (A, B, C) and one-output (O) multiterminal fan-in CVD Gr circuit with ferromagnetic electrodes ( $Co / {Ti O}_{2}$ , blue color). Type of injected spin polarization, spin up (1) or spin down (0), can be controlled by changing the magnetization of electrodes or by applying electrical bias currents of opposite polarities (+I or −I) to achieve spin injection or extraction. Resultant spin state is probed as an output voltage signal after spin transport and mixing in the graphene buses. Nonmagnetic electrodes ( $Au / Ti$ , yellow) are used as reference contacts. (c) Simulation comparing the output signal of a conventional charge-based majority gate and a spin-majority logic device for different combinations of input states. Majority gate logic output is true (or 1) when half or more arguments are true; otherwise it is false (or 0). To simulate the device, spin-circuit models employ conductance matrices, G, to capture spin transmission through FM/Gr interfaces and spin diffusion and relaxation in graphene. Spin-based realization shows multiple signal levels, which provide additional information on the number of inputs that constitute the majority.
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Figure 2
Spin communication in the graphene circuit. (a) Schematic with a measurement geometry for characterizing spin transport in graphene branches A, B, and C. (b) Gate dependence of the graphene channel resistance in each branch. (c),(d) Spin-valve and Hanle spin-precession measurements for each channel with inputs from A, B, and C with magnetic field sweeps in B_y and B_z directions, respectively. Measurements are performed for parallel (P) and antiparallel (AP) magnetic orientations of input and output ferromagnetic contacts. Measurements are performed with a bias current of I = −200 µA. (e) Bias dependence of the spin-valve signal magnitude (V) for each injector. Gray horizontal lines represent the selected output voltage level (limited by the nonlinearity observed for injectors A and C), and corresponding vertical lines determine the values for positive and negative bias currents used in majority logic measurements. All the measurements are performed at room temperature.
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Figure 3
Spin mixing in a two-input fan-in device. (a),(b) Spin-valve signals obtained using individual inputs A and B, and spin-addition or spin-cancellation operations performed by simultaneously injecting spins from both branches of the device. (c),(d) Output spin voltage at the detector as a function of time; panels show spin-circuit-based simulation and experiment, respectively. (e) Sequence of the applied bias currents to the two input contacts A and B. (f) Device performance over several cycles. All the measurements are performed at room temperature.
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Figure 4
Spin-majority logic operation with the three-input fan-in device. (a) Schematic of the spin-majority logic device, where all three spin inputs (A, B, C) are used simultaneously, and the majority of the injected spin polarizations define the nonlocal output (O) spin voltage. (b) Truth table for a majority gate. Output is true when at least two of the inputs are true. By fixing any of the inputs as 0 or 1, the output for the remaining two inputs represents an and or or operation, demonstrating the reconfigurability of the gate. (c),(d) Spin-circuit-model-based simulation and experimental realization, respectively, of the spin-majority logic device achieved by applying a sequence of the pulse bias currents to all inputs [I_A, I_B, I_C, panel (e)] as a function of time to probe all possible logic states. +I results in spin injection and −I leads to spin extraction. (f) Device performance over several cycles. All the measurements are performed at room temperature.
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