Abstract
This paper introduces the design of a l.8 V low dropout voltage regulator (LDO) and a foldback current limit circuit which limits the output current to 3 mA when load over-current occurs. The LDO was implemented in a 0.18 μm CMOS technology. The measured result reveals that the LDO's power supply rejection (PSR) is about −58 dB and −54 dB at 20 Hz and 1 kHz respectively, the response time is 4 μs and the quiescent current is 20 μA. The designed LDO regulator can work with a supply voltage down to 2.0 V with a drop-out voltage of 200 mV at a maximum load current of 240 mA.