Performance enhancement of GaSb vertical nanowire p-type MOSFETs on Si by rapid thermal annealing

The transfer characteristics of the individual GaSb NW MOSFET in each sample before and after RTA at different temperatures are shown in figure 2. In consideration of the change in threshold voltage (V_T) after RTA (see supplementary material: figure S1 (available online at stacks.iop.org/NANO/33/075202/mmedia)), the gate overdrive voltage, V_OV = V_GS–V_T, is presented in this article instead of the absolute gate bias V_GS for better comparison. Generally, as compared to the as-fabricated device performance, the drain current (I_DS) as well as g_m increases after RTA and reaches a maximum after annealing at 300 °C in both samples. Further increasing the RTA temperature up to 350 °C, however, degrades the on-state performance in both samples. In S1, an increased on-current (I_on, defined at V_OV = −0.5 V) of 31 μA μm⁻¹ as well as a peak g_m (g_m,peak) of 70 μS μm⁻¹ at V_DS = −0.5 V are achieved in the device after RTA at 300 °C with corresponding increment of ∼25% as shown in figures 2(a) and (b), respectively. However, the source depletion of the device in S1 becomes severe after annealing at 350 °C probably due to higher efficiency in hydrogen passivation at the InAs/high-k interface than that in GaSb/high-k interface so that InAs bands adjacent to the junction move up faster than GaSb bands at high negative gate bias. As a result, the tunneling probability between InAs and GaSb may be reduced, thereby lowering the drain current. Despite a thicker oxide layer including both the high-k and the bottom spacer (Al₂O₃) on the InAs segment, substantially lower D_it at the interface of InAs/high-k likely results in high gating efficiency at high gate voltage. Several reports have shown that the optimal annealing temperature of hydrogen passivation of In(Ga)As/high-k interface is close to 350 °C [31, 32]. Therefore, annealing at lower temperatures has relatively limited effects on InAs/high-k interface passivation, resulting in less source depletion.

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Thanks to a shorter L_g, S2 provides a better on-state performance in both I_DS and g_m,peak, but meanwhile higher overdrive bias (∼0.2 V higher in V_OV) is needed to achieve g_m,peak as compared to S1, seen in figures 2(b) and (d). Thus, to reflect this difference, we defined I_on at relatively higher V_OV (−0.7 V) for S2. Here, as the comparison of I_on only occurs before and after RTA in the same sample, I_on may well be defined independently between two samples. In S2, despite only 20% increase in I_on, g_m,peak is enhanced by almost 50% up to 149 μS μm⁻¹ after RTA at 300 °C.

Figure 3 shows the corresponding statistical results based on 28 single NW devices in both S1 and S2, as a function of RTA temperatures. In the case of S1, the median values of I_on and g_m,peak determined at different RTA temperatures are compared in figures 3(a) and (b), respectively, showing an unambiguous enhancement with increasing the annealing temperature from 200 °C to 300 °C whereas maintaining almost the same value when further increasing the temperature to 350 °C. In figure 3(b), g_m,peak increases 50% on average after RTA at 300 °C compared to as-fabricated devices, reaching a maximum median value of 42 μS μm⁻¹. It is noticeable that when increasing the RTA temperature, the minimum g_m,peak increases more than 100% and it follows the same trend as the median value while the maximum g_m,peak increases roughly 10%. Therefore, the g_m,peak increase mainly results from the enhancement in those devices with low as-fabricated g_m,peak. However, after annealing at 350 °C, those devices start degrading again, resulting in a reduced minimum value in both I_on and g_m,peak. Thus, the spread of the data set after annealing at 300 °C is narrowed but widened again when annealing at 350 °C due to the device degradation. In addition, a similar feature of I_on change with the RTA temperature is shown in figure 3(a).

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Figure 4(a) compares the output characteristics of the same devices plotted in figure 2 before and after RTA. Here, only the output curve at V_OV that defines I_on is selected to present for both samples, respectively. For the individual devices in S1 and S2, R_on first decreases when annealing at 300 °C, reaching 16.7 kΩ·μm and 4.7 kΩ·μm in the device of S1 and S2, respectively, but increases again after RTA at 350 °C. Similar as the individual devices, the corresponding statistical result of R_on in S1 shows decreasing R_on as increasing the RTA temperature until 300 °C, presented in figure 4(b). In spite of the large variation in R_on, it is found that the median R_on of all devices annealed at 300 °C is still reduced 26% as compared to that without annealing. In contrast to the clear drop in R_on after RTA observed in S1, no noticeable change of R_on is observed in S2 in the same RTA temperature interval, shown in figure 4(c). Instead, almost identical median value and device variation are obtained with increasing RTA temperature until 300 °C. Among the 28 studied devices in S2, there are 12 devices with a higher R_on after RTA at 300 °C and 16 devices having a lower value. Although the maximum reduction reaches 33%, most of the devices have a change within ±10%, leading to a similar median value after RTA. As compared to S1, a 7-times lower mean R_on (6.5 kΩ·μm) is achieved before annealing in S2, while the gate length is only 2.5 times shorter. Hence, the top contact is likely improved with W–InAs/GaSb configuration, thereby contributing to significant R_on reduction in S2.

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It is reasonable to assume that the access resistance will remain constant when annealing at such moderate temperatures (200 °C–350 °C). The access resistance is mainly determined by the geometry and the carrier density, which relates to the doping concentration in this case. Since the epitaxial growth temperature of the NWs is much higher than the annealing temperatures, the doping profile should be unchanged after RTA. Therefore, we believe that the R_on reduction in S1 after RTA can be mainly interpreted as the improvement of the top contact in the NW transistors. Annealing can promote Ni to alloy with GaSb, leading to more Ni–GaSb alloy formed at high temperature thus lowering the sheet resistance of Ni–GaSb alloy layer [7, 24]. Extrapolating to the transistor level, the contact resistance can be lowered by forming higher conducting Ni–GaSb alloy after annealing. However, higher annealing temperatures may degrade the contact attributed to the presence of a new phase Ni₂Ga₃ (forming at 369 °C according to the phase diagram [33] with higher resistivity in the alloy while the desired NiGa(Sb) phase is only formed at relatively low annealing temperature [25]. Consequently, a slight increase in R_on occurs after RTA at 350 °C in S1.

Despite unchanged median value and variation in statistical result of R_on in S2, a small variance within 10% is still found in most of the devices. R_on increasing or decreasing in this case could be attributed to the relatively slight change in the top contact which is W–InAs/GaSb in S2. W is used as a non-alloy ohmic contact for InGaAs transistors [4] and behaves similarly as Mo [28] for contacting InGaAs. Moreover, a recent study on InGaAs VNW devices with Mo–InGaAs (similar as W–InGaAs) non-alloy contact shows a smaller change in R_on with varying RTA temperatures as compared to Ni–InGaAs transistors [23]. Thus, W–InAs/GaSb likely provides a rather thermally stable contact below 300 °C as compared to Ni–GaSb. However, we observed a dramatic increase in not only the median value but the spread of R_on after RTA at 350 °C, which may highly relate to the deterioration in channel interface thus leading to a dominantly large channel resistance as compared to considerably low contact resistance in S2. The annealing effects on the interface will be discussed in the next section

Figure 5(a) presents the statistics of saturation SS (SS_sat, at V_DS = −0.5 V) with varying RTA temperature. For S1, SS_sat continuously reduces when increasing the annealing temperature even up to 350 °C. Specifically, the reduction in SS_sat is mainly determined by the improvement of devices with originally high SS, thus a narrower distribution is achieved, reaching a lowest SS_sat = 166 mV dec⁻¹ in a device as shown in figure 5(b). A similar trend based on statistics is observed for SS_lin (see supplementary material: figure S2(a)) and a minimum value of 144 mV dec⁻¹ is obtained in the same device shown in figure 5(b), which is the lowest subthreshold swing among reported GaSb-based p-MOSFETs [8, 17, 19, 34]. In accordance with the equation [35] $SS\approx (kT/q)\cdot \,\mathrm{ln}(10)(1+q{D}_{{\rm{it}}}/{C}_{{\rm{ox}}}),$ where k is the Boltzmann constant, T the temperature, q the electron charge and C_ox the capacitance of the high-k oxides which is assumed to be invariant with annealing [36]. D_it refers to the trap density of the MOS interface, usually describing the interface quality. The lower D_it, the better interface quality. Based on this equation, the change of SS can be determined by D_it only. Thus, we estimated D_it ≈ 3.6 × 10¹³ eV⁻¹ cm⁻² at V_DS = −0.05 V after annealing by calculating a coaxial oxide capacitance of C_ox ≈ 7 aF nm⁻¹. By considering the same device before annealing, D_it approximates to 4.4 × 10¹³ eV⁻¹ cm⁻², thus indicating a reduction of 22%. Therefore, the reduction in SS can originate from the MOS interface improvement by lowering D_it attributed to the H₂ passivation capability during RTA.

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In contrast, S2 exhibits an opposite trend of SS_sat (also see SS_lin trend in supplementary material: figure S2(a)) with RTA temperature, showing a significant increase after annealing at 300 °C–350 °C. Although S2 has a higher SS_sat than S1 before RTA, a similar drain-induced barrier lowering is found in S1 and S2, suggesting a good electrostatic control without short channel effect when scaling down L_g from 200 to 80 nm. Therefore, the high SS before RTA in S2 mainly results from the increase of D_it at the channel interface as compared to that of S1 fabricated with the gate-first process. For the gate-last process in S2, many additional steps are required prior to the digital etching and subsequent high-k deposition, resulting in unexpected process-induced contaminations. One likely contamination of the channel can be oxygen vacancy from residual GaSb oxides present from the digital etching. The first 30 s ozone treatment at 50 °C is likely to oxidate through the InAs shell and deeply penetrate into GaSb to form a thick GaSb oxide layer [37] which may be insufficiently etched by HCl:IPA for 30 s in the current process. The presence of oxygen vacancy at the interface may generate more traps at the GaSb/high-k interface thereby increasing SS. Although these oxygen vacancies might be reduced by annealing in an ambient with hydrogen, other possible contamination originating from the previous process would be active to react with the channel surface when annealing, probably leading to more interface states. Thus, the dramatic increase of SS after RTA is likely related to these interface states activated by annealing. As a result, D_it increases substantially after RTA at 300 °C or higher, leading to a poor off-state performance. Further detailed material characterizations for the channel interface in our NWs, such as x-ray photoelectron spectroscopy and transmission electron microscopy, are needed to verify of our hypothesis.

The off-state performance in S1 is further studied. The device with lowest SS after RTA at 350 °C also reveals a high on/off current ratio (I_on/I_off) over 1000 with attractive I_on = 23 μA μm⁻¹ and a low I_off = 19 nA μm⁻¹ at V_DS = −0.5 V, as demonstrated in figure 5(b). In figure 5(c), a stable I_off = 40 nA μm⁻¹ retains until annealing at 300 °C and further reduces to 30 nA μm⁻¹ after RTA 350 °C. In addition, the minimum drain current (I_DS,min) fluctuates with RTA temperatures in a small range around ∼10 nA μm⁻¹. The lowest I_DS,min in all studied devices at off-state reaches 4 nA μm⁻¹ after annealing at 200 °C and 250 °C, which fulfills the I_off specification of the International Technology Roadmap for Semiconductors low operation power application (5 nA μm⁻¹) [38]. In addition, approximately 50% increase in I_on/I_off is attained after RTA at 350 °C attributed to both I_on increase and I_off reduction with respect to as-fabricated performance as shown in figure 5(d). On the other hand, only I_on increase accounts for the gradual increase in I_on/I_off when the annealing at 200 °C–300 °C. The results of S1 show the best balance in on- and off-state performance among recently reported GaSb-related transistors [10, 18, 39], indicating an attractive potential for low power logic applications. In contrast, the off-state performance degrades significantly after RTA process in S2 as both SS and I_off (see supplementary material: figure S2(b)) increase with annealing temperatures.

Based on the analysis in the previous sections, it is evident that RTA at 300 °C provides the best performance improvement with annealing in both S1 and S2. Thus, table 2 summarizes the improvements and changes in each sample after RTA at 300 °C with respect to the as-fabricated performance. For S1, the improvements of not only the top contact but the channel interface after RTA lead to the reduction in both R_on and SS, thus in turn contributing to an enhancement of g_m,peak by 50% on average. Surprisingly, for S2, g_m,peak achieves 20% increment after annealing whereas R_on keeps invariant and SS deteriorates due to more unexpected contamination in S2. In spite of an invariant R_on on average, slight change still exists in individual devices (see supplementary material), where those devices with reduced R_on, the g_m,peak increase linearly depends on the reduction in R_on. Therefore, the reduction of R_on could be the unique contribution to the g_m,peak increase, leading to less improvement in percentage of g_m,peak for S2 as compared to S1. The detailed correlation of g_m,peak, R_on and SS regarding on individual devices in both samples is shown in supplementary material: figures S3 and S4.

The average change reflects the similar conclusions as discussed previously. For S1, it is difficult to significantly improve the top contact and channel interface at the same since effectively improving MOS interface usually requires a higher annealing temperature (approximately 350 °C) [40, 41], which could degrade the top contact of the device (increasing R_on) by changing the Ni–GaSb alloy structures as addressed previously. One feasible option to further improve GaSb NW MOSFETs by annealing is probably to include both forming gas (N₂/H₂) annealing directly after gate metal deposition for the MOS interface at a higher temperature and another annealing process at a relatively lower temperature after fabrication to only improve the contacts [41]. For S2, the key issue is the high SS which likely results from the process-induced contamination, being strongly degraded by RTA. However, the impressive improvement in g_m exists in those devices with high as-fabricated performance in S2. Thus, although using the characteristics of S2 for digital applications may be challenging, for some RF applications [28] or the current source of all-III-V platform, a high SS can still be acceptable. Further gate-stack development can also help to improve SS.

Table 3 and figure 6 benchmark this work with recently published GaSb-related p-type MOSFETs with L_g < 500 nm. 3 different VNW devices from S1 after annealing are included in table 3, all showing a good off-state current below 10 nA μm⁻¹ simultaneously along with a competitive I_on, showing a great balance in on- and off-state performance. We have also achieved a record SS among all GaSb-based sub-500 nm p-type MOSFETs, verifying a great electrostatic control with the gate-first process. For the benchmarking of g_m,peak versus L_g in figure 6, comparing to the performance of not annealed devices, the annealed devices in both S1 and S2 have been improved and both approach the position in line with the gate length scaling in state-of-the-art GaSb-based transistors.

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