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Parallel merge algorithm for high-throughput signal processing applications

Parallel merge algorithm for high-throughput signal processing applications

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© The Institution of Engineering and Technology
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A parallel merge algorithm is proposed that results in a smaller critical-path delay than all of the other merge algorithms explored. The parallel merge circuit effectively increases the throughput of VLSI signal processing systems. The critical path of this circuit is independent of the number of input values.

Inspec keywords: VLSI; signal processing

Other keywords: high-throughput signal processing applications; VLSI signal processing systems; parallel merge algorithm; critical-path delay

Subjects: Signal processing and detection; Semiconductor integrated circuits

References

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      • Batcher, K.E.: `Sorting networks and their applications', AFIPS Proc. on Spring Joint Computer Conf., 1968, Atlantic City, NJ, USA, p. 304–314.
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      • Burg, A., Borgmann, M., Wenk, M., Studer, C., Bölcskei, H.: `Advanced receiver algorithms for MIMO wireless communications', IEEE Design, Automation, and Test in Europe (DATE), March 2006, Munich, Germany, p. 593–598.
    3. 3)
      • D.E. Knuth . (1973) The art of computer programming, Sorting and searching.
    4. 4)
      • Wenk, M.: `K-best MIMO detection VLSI architectures achieving up to 424 Mbps', Proc. IEEE ISCAS, May 2006, Kos, Greece, 3, p. 1151–1154.
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