Introduction

Thin film transistors (TFTs) with disordered channel layers comprising say amorphous oxide or organic semiconductors, are becoming ubiquitous especially where low temperature processability and flexibility are essential1,2,3. To facilitate TFT systems design, a complete understanding on device physics and related device parameter extraction constitutes the first and inevitable step. In this vein, the work presented here on conduction threshold is a very fundamental device parameter. The work is applicable not only to thin film field effect transistor (FET) but also the pervasive silicon metal-oxide-semiconductor FET (MOSFET). Given its significance as a crucial indicator of carrier transport and instability in FETs4,5,6,7,8,9,10, the conduction threshold has to be determined physically rather than by empirical means11.

Silicon MOSFETs conduct in inversion mode and the physical reason underlying the conduction threshold is well understood4,5. It corresponds to the critical state in which the induced or (inverted) carrier density becomes the same as the substrate’s majority carrier density5. For example, in an n-channel MOSFET, this transition point is when the electron density goes from linear to exponential dependence on energy in the solution of the Poisson-Boltzmann equation 5. This transition can be approximated empirically as the intercept made from a linear extrapolation on the drain current (IDS) vs. gate voltage (VGS) characteristic at very low drain voltage (VDS)5.

In contrast to the silicon MOSFET, the TFT works in carrier accumulation mode regardless of the channel material6,7,8,9. This means that there is no polarity inversion of the induced carriers, so it is difficult to physically define the accumulation threshold. Moreover, because of the structural disorder of the semiconductor channel layer, there are localized deep and tail states distributed within the so-called band-gap and depending on the position of the Fermi-level, free carriers or trapped carriers can be prevalent12,13. As a result, the conduction threshold is difficult to extract even empirically6,14,15,16. The density of carriers trapped at these localized states can be greater than free carriers and there is no physical criteria for which all the traps are filled. In this family of devices, it is the localized trap states that determine the behaviour of field-effect mobility as a function of gate bias.

In this letter, we present a systematic analysis of the conduction threshold leading to a physical definition of the threshold voltage in accumulation-mode InGaZnO TFTs. By solving the Poisson-Boltzmann equation coupled with measurements of the current-voltage characteristics, the total carrier density is captured as a function of the surface potential. Similar to the MOSFET, it turns out that there is a transition point in which the accumulated carrier concentration switches from a linear to an exponential dependence on energy, i.e. the free carrier density increases rapidly from this threshold level by virtue of trap-limited conduction. We find that this threshold can be directly extracted as the gate voltage in which the second derivative of IDS with respect to VGS peaks. This is visualized with the proposed grayscale image spectroscopy, allowing an ease of analysis on threshold voltage and related properties. The studies presented here show that the conduction threshold is independent of the band mobility and is largely determined by the sub-threshold characteristics associated with the deep states including interface states.

Results and Discussion

Microscopic conduction threshold

For the investigations reported here, we used a semiconducting oxide TFT test structure with a 50 nm thick InGaZnO channel layer, as seen in Fig. 1(a,b). The device is a typical bottom gate structure where Mo is used for electrodes. Here, the gate insulator is formed as a bilayer of SiOx and SiNx and the total gate-insulator capacitance of this structure (Cox) is ~10 nF/cm2. As a final step, a single layer of SiOx is used for passivation layer and etch-stop layer (ESL). The TFT has a 50 μm channel width (W) and 10 μm channel length (L). Its IDS vs. VGS measured for VDS fixed at 10 mV is shown in Fig. 1(c,d). Here, we retrieve an effective flat-band voltage (VFB) of 0.3 V and a sub-threshold slope (SS) of 0.32 V/dec. Using the measured IDS − VGS characteristics, the microscopic picture in terms of free and trapped carrier densities can be captured as a function of VGS. The free charge density (Qfree) relates to the drain current as12,13,

Figure 1
figure 1

(a) Photomicrograph and (b) schematic of the fabricated InGaZnO TFTs examined in this work. Measured drain current (IDS) vs. gate voltage (VGS) in (c) linear scale and (d) log scale, respectively. Here, we indicate an effective flat-band voltage ~0.3 V.

where μb is the band mobility. Equation (1) is valid for both sub- and above-threshold regimes as long as VDS < kT/q, where kT thermal energy and q the elementary charge (see Supplementary Information S1). In addition, we replace VDS with VDS − RCIDS, where RC is a contact resistance. The value of RC retrieved for the test structure considered here is 50 kΩ. The main-unknown in Equation (1) is μb, which typically ranges from 10 to 30 cm2/V-s7,9. From Equation(1) and the measured IDS − VGS, Qfree can be stated as a function of VGS and related with the free carrier density (nfree) through Qfree = q nfreeλfree. Here, λfree is an effective thickness of the induced free carrier sheet and is expressed as an harmonic average between the free carrier Debye length (λD) and thickness of In-Ga-Zn-O channel layer (tS), viz. λfree = (λD−1 + tS−1)−1, assuming that the penetration depth of the vertical electric field is limited within tS17,18. The λD can be obtained using εSkT/(qQfree)5,16, where εS is the permittivity of the In-Ga-Zn-O channel layer. The value of λfree is shown in Fig. 2(a). From this, we express nfree as Qfree/(qλfree), which is still a function of VGS, i.e. nfree(VGS). To express it as a function of surface potential (φS), we relate this to Boltzmann’s equation, i.e. nfree = NC exp[(EF0 + qφS – EC)/kT]5,12. Here, NC is the effective density of free carriers, EF0 an equilibrium Fermi level and EC the energy level of the conduction band minima. For the device considered here, NC is ~2 × 1018 cm−3. We now have a correspondence between VGS and φS,

Figure 2
figure 2

(a) Effective thickness of induced free carrier sheet (λfree) vs. VGS. (b) Surface potential (φS) as a function of VGS and (c) total induced carrier density (ntot) and nfree as a function of φS for different μb values of 10, 20 and 30 cm2/V-s, respectively.

Using Equation (2), φS is computed for three different values of μb, which is contained in nfree(VGS). This is shown in Fig. 2(b).

Now, we solve the integral form of Poisson’s equation, which yields the relationship between the surface electric field (ES) and integral of total accumulated carrier density ntot for φS as follows12,

For more detailed derivation, see Supplementary Information S2. In addition, we have expressed the left hand side of the Equation (3) as a function of VGS, i.e. ES = Cox(VGS − VFB)/εS ≡ g(VGS) by virtue of Gauss’ Law (see Supplementary Information S3). Based on Equations (2) and (3), ntot can be written as,

in which ntot is nfree + ndeep + ntail. Here ndeep and ntail are the densities of carriers trapped in deep and tail states, respectively. In the term, ndeep, the effect of carriers trapped at the interface states is embedded since ndeep consists of defect state carriers at the bulk (i.e. nbulk) as well as interface (i.e. nint), thus ndeep = nbulk + nint13,17. Equation (4) can be considered as a differential form of the Poisson-Boltzmann equation, allowing examination of the behaviour of carrier densities ntot with φS, as depicted in Fig. 2(c) in a semi-log plot. A transition is observed at φS = 0.25 V, for a corresponding gate voltage of 1.74 V, whereby the carrier density ntot goes from linear to an exponential dependency on energy. Based on this observation, we can define the threshold voltage (VT) of the device as 1.74 V, which corresponds to the transition surface potential (φT) of 0.25 V. The physical meaning underlying this transition is further discussed in the following.

From Fig. 2(c), we find that the trapped carriers are dominant for all energy levels, i.e. nfree < ntail + ndeep, thus trap-limited conduction (TLC) always prevails. Depending on the value of φS, the one or the other can prevail. For example, below φT, ndeep prevails and the linear dependency of ntot can be explained as,

where ζd is a deep state density related to either nbulk or nint. From Fig. 2(c), the value of ζd in the examined InGaZnO TFT is estimated as ~2.1 × 1016 cm−3 eV−1. Besides, ζd can also be retrieved from the relation Cdeep/(q2tS), where Cdeep is a deep state capacitance, which can be deduced independently from the sub-threshold slope (SS) through the relationship, Cdeep = Cox [SS/(kT/q·ln10) – 1]17. For the channel thickness considered here (tS = 50 nm), Cdeep ~ 43.7 nF/cm2, yielding ζd ~ 3 × 1016 cm−3 eV−1. It is consistent with the value empirically estimated using Fig. 2(c). Note that, along with the Cdeep and φT, an analytical expression of threshold voltage (VT) can be derived from the charge neutrality equation, Cox(VT − VFB − φT) = CdeepφT, yielding as,

With Equation (6), VT is estimated as 1.64 V using Cdeep ~ 43.7 nF/cm2, Cox ~ 10 nF/cm2, φT = 0.25 V and VFB = 0.3 V. Although it may be inaccurate due to its approximation to be analytical, Equation (6) can allow a quick estimation of VT. Also, it is useful to see its proportionality with deep states (i.e. bulk and interface states) through the term, Cdeep, for example.

After the transition (φT = 0.25 V), ntail prevails. Indeed, the carrier density now increases exponentially, seen as linear on the semi-log plot Fig. 2(c). And it can be described by the following relation for kTt > kT12,16,19,

where Ntc is the tail state density at EC and kTt is the characteristic energy of tail states associated with the exponential profile of the energy of the band tail states6,12,14,16,19. As seen in Fig. 2(c), the transition is always maintained as an intersection point regardless of the assumed value of μb.

To check the relationship between the transition point and electronic states for electrons, we deduce the density of states using the values of ntot and nfree (see Fig. 2(c)), through12,

Here, the Fermi level EF replaces φS by virtue of the relation, EF − EF0 = qφS. Figure 3 shows the profile of the density of states as a function of energy while assuming μb = 20 cm2/V-s. We identify a transition energy ET that demarcates the deep and tail states, confirming that all the deep states (Ndeep) are filled when EF arrives at ET (see also the inset of Fig. 3). This demarcation defines the threshold voltage. Based on this observation of ET, it is expected that ET can move toward a higher energy when Ndeep is increased while maintaining the profile of tail states, resulting in a higher VT (see Supplementary Information S6). As seen in Fig. 3, at energies higher than ET, the tail state distribution is found to follow an exponential dependence, i.e. Ntail(E) = Ntcexp[(E − EC)/kTt]6,12,16. Using the exponential dependence of the tail states, the retrieved values of Ntc and kTt are ~1020 cm−3 eV−1 and 27 meV, respectively, as seen in Fig. 3. Thus kTt > kT at T = 300 K. This confirms that the TLC is dominant at T = 300 K. Besides, the exponent (α) in the power-law for the IDS − VGS curve above VT is defined as 2 kTt/kT – 1 for kTt > kT6,12,14,20. The value of α at T = 300 K is about 1.07 for kTt = 27 meV, which consistent with the observed linear dependence of IDS on VGS as seen in Fig. 1(c). As implied here, the role of Ntc and kTt is important in the TFT conduction, relating to the material composition. For example, with decreasing the ratio of In/Ga, field effect mobility of In-Ga-Zn-O TFTs can be reduced, suggesting a higher density of tail states (Ntc)21,22. In other words, if Ntc is higher, EF can be pinned at a lower energy from the conduction band minima (see Supplementary Information S6). This leads to a lower mobility reminiscent of the a-Si TFT whereas Fermi level in oxide TFT can even go into the conduction band due to its lower tail state density23.

Figure 3
figure 3

Density of states as a function of energy from EC.

Inset: band diagrams for three different cases of transition energy (ET): below ET, at ET and above ET. Here, EV denotes the valence band maxima and Ndeep(E) and Ntail(E) the respective density of deep and tail states as a function of energy.

Based on the characteristic behaviour of the carrier densities shown in Fig. 2(c), the significance of the free carrier density (nfree) relative to the total carrier density (ntot = nfree + ndeep + ntail) can be defined as a ratio (χTLC) in accordance to the TLC theory6,14,16,

Using Equation (8) together with the values shown in Fig. 2(c), the behaviour of χTLC and its first derivative with respect to VGS (i.e. ∂χTLC/∂VGS) as a function of VGS is shown in Fig. 4(a,b), respectively. We see that ∂χTLC/∂VGS peaks at VGS ~ 1.74 V regardless of the value of μb. This is consistent with our earlier observation of the common intercept seen in Fig. 2(c). Indeed, χTLC shows a similarity with the first derivative of the current-voltage characteristics, ∂IDS/∂VGS, as seen in Fig. 4(a,c). As it turns out, ∂IDS/∂VGS is the trans- conductance of the transistor, which in turn is proportional to the field effect mobility (μFE). Thus, μFE is proportional to χTLC. Indeed in accordance with the TLC theory, μFE can be defined as μb nfree/ntot = μb χTLC6,20,24. At high VGS, the behaviour of ∂IDS/∂VGS without effect of RC looks similar to χTLC for μb = 20 cm2/V-s (see Supplementary Information S4). This suggests that μb of the examined device is ~20 cm2/V-s. The similarity between ∂χTLC/∂VGS and the second derivative ∂2IDS/∂VGS2 becomes even more striking in which the peak is at 1.74 V regardless of the band mobility (μb) values assumed for this analysis (see Fig. 4(b)). More importantly, the experimentally observed peak in ∂2IDS/∂VGS2 vs. VGS appears at ~1.76 V which corroborates with theoretical prediction with a discrepancy less than 2%, as seen in Fig. 4(d). From the nature of the ∂2IDS/∂VGS2 curve, we clearly identify the roles of deep and tail states, respectively, on either side of the peak where the threshold voltage lies. The deep states and corresponding sub-threshold slope determines the slope of the rising edge while the tail states and its exponent α are associated with that of the falling edge (see Fig. 4(d)).

Figure 4
figure 4

(a) Trap-limited conduction (TLC) ratio (χTLC) as a function of VGS. (b) The first derivative of χTLC with respect to VGS. (c) The first derivative (i.e. ∂IDS/∂VGS) and (d) second derivative (i.e. ∂2IDS/∂VGS2) of IDS vs. VGS.

Macroscopic observation of the threshold

The above analysis can be extended to measurements of device behaviour at different temperatures. Figure 5(a) shows IDS − VGS characteristics at T = 300 K, 200 K, 100 K and the ∂2IDS/∂VGS2 in each case is shown in Fig. 5(b). As the ambient temperature decreases, we observe that VT shifts to more positive VGS values. This is because of reduced thermal activation12. As temperature decreases, the current-voltage characteristic approaches a more power-law behaviour, as indicated in Fig. 5(a). Consequently, its second derivative converges to a non-zero value for VGS > VT and which increases with decreasing temperature, as seen in Fig. 5(b). This is mainly associated with the tail state exponent (i.e. α = 2 kTt/kT–1), which increases with decreasing temperature. In contrast, the rising edge becomes increasingly steeper at lower temperatures, as indicated in Fig. 5(b). This is mainly due to the smaller sub-threshold slope (SS) at lower temperatures, which is typical of field effect transistors and can be intuitively explained with the relation, SS = ln(10)·kT/q(1 + Cdeep/Cox)17, assuming Cdeep is independent of temperature.

Figure 5
figure 5

(a) Measured IDS vs. VGS for three different temperatures (T = 300 K, 200 K and 100 K). (b) Normalized ∂2IDS/∂VGS2 for different temperatures. (c) Three curves of IDS vs. VGS measured before and after +20 V positive bias stress (PBS) for 500s and 1000s, respectively. (d) Normalized ∂2IDS/∂VGS2 for different bias stress times. Note that each ∂2IDS/∂VGS2 has been normalized to its peak value.

The observations of the current-voltage characteristics and its second derivative presented hitherto considerably simplify the interpretation of the shift in threshold voltage in bias stress experiments. More importantly, the shift in VT can be retrieved with minimizing an interruption to the stress measurement conditions. Figure 5(c) shows the measured IDS − VGS characteristics following positive bias stress (i.e. PBS at VGS = +20 V while maintaining VDS = 0 V) for stress durations (tPBS) of 500 sec and 1000 sec. As seen in Fig. 5(d), there is a positive VT-shift, which increases with stress duration. Since the value of ∂2IDS/∂VGS2 in a well-above VT regime remains zero for all cases, as seen in Fig. 5(d), it suggests that there is no significant degradation in band tail states (e.g. kTt), thus unaffecting the tail state exponent α. This suggests electron trapping into the gate insulator as the significant and likely source of VT-shift. However, the ∂2IDS/∂VGS2 curve appears to spread out more for longer tPBS. Indeed, the slope of the rising edge (at VGS < VT) becomes less steep, suggesting creation of deep defects25,26,27. Since the slope of falling edge decreases, as seen in Fig. 5(d), it can be argued that tail states are newly created near ET (see Supplementary Information S5). So, it is obvious that the analysis presented here is especially useful under bias stress, as it is indicative of the nature of defects created in the sub-threshold and above-threshold regimes.

As another outcome of the presented analysis, we propose an image spectroscopy constructed from the second derivatives, as seen in Fig. 5. This method allows a visualization of VT position as well as a property change near VT. As an example, Fig. 5(a) shows IDS − VGS characteristics measured at different ambient temperatures (300 K, 200 K, 100 K) and the VT for each case is visualized in a grayscale image, as indicated in Fig. 6(a). Here, it is found that VT is shifted to more positive in VGS as decreasing temperature. Besides this, it is also observed that the grayscale image above VT is getting brighter as decreasing temperature. This confirms that IDS − VGS curvature in on state (i.e. above-threshold regime) becomes more nonlinear, as can be seen in Fig. 5(b). As another example, it can be applied to analyze the VT instability with respect to bias stresses. In Fig. 5(c), we show the measured IDS − VGS curves after applying a positive bias stress (VGS = +20 V while VDS = 0 V) for 500 sec and 1000 sec, respectively. As clearly seen in the constructed grayscale image (see Fig. 6(b)), there is a positive VT shift and its increase towards more positive direction in VGS with a longer stress time (tPBS). Since the on state image brightness for each case looks dark and similar each other, as seen in Fig. 6(b), we can say that there isn’t a significant degradation in band tail states which represents above-threshold regime (i.e. on state) curvature. So, this can be explained with electron trapping into gate insulator. However, the bright parts near VT appear to spread out more after applying the PBS with a longer tPBS. This suggests that the sub-threshold slope has been slightly bigger and tail states are newly created near ET. This is consistent with the results in Fig. 5(d).

Figure 6
figure 6

Grayscale images constructed from ∂2IDS/∂VGS2 (a) for different temperatures and (b) for different stress durations, respectively.

Conclusions

The channel layer in amorphous thin film transistors in accumulation mode generally suffer from structural disorder resulting in localized deep and tail states in the energy gap. This makes the classical empirically-based extraction of the conduction threshold difficult, if not ambiguous, since depending on the Fermi level, conduction of free or trapped carriers can be prevalent determined by the shape of the localized tail states. This paper resolves the ambiguity in interpretation of the conduction threshold in accumulation-mode InGaZnO thin film transistors and provides a quantitative means of uniquely extracting the threshold voltage. The conduction threshold has been identified to take place at the transition of the Fermi level from deep to tail states, following which the carrier density goes from a linear to exponential dependence on energy. While the analysis presented here can be applied to study the relative changes in deep defects and tail states at pre- and post-transition caused by effects of ambient temperature and bias stress, a more precise analytical description is needed to quantitatively assess and subsequently predict the nature of the density of states when subject to environmental factors. Work along these lines is in progress. Nevertheless the results demonstrated here give physical and quantitative insight into the VT and related properties in accumulation-mode thin film transistors.

Additional Information

How to cite this article: Lee, S. and Nathan, A. Conduction Threshold in Accumulation-Mode InGaZnO Thin Film Transistors. Sci. Rep. 6, 22567; doi: 10.1038/srep22567 (2016).