Correction to: Scientific Reports https://doi.org/10.1038/s41598-021-94691-7, published online 28 July 2021
The original version of this Article contained an error in Figure 3 where panels (b) and (c) were incorrectly captured. The original Figure 3 and accompanying legend appear below.
(a) Example of 6 8-bit inputs FLP adder tree. (b) Architecture of a FLP adder. (c) Architecture of the optimized FLP adder used in the first level of the tree.
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Cardarilli, G.C., Di Nunzio, L., Fazzolari, R. et al. Author Correction: A pseudo-softmax function for hardware-based high speed image classification. Sci Rep 11, 17767 (2021). https://doi.org/10.1038/s41598-021-97079-9
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DOI: https://doi.org/10.1038/s41598-021-97079-9
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