Introduction

In recent decades, the modernization of individuals and the development of renewable energy technology are increasing worldwide, driven by the alert on global warming. To reduce CO2 emission and generate more electricity to meet demand, the solar energy system is an important option capable of generating power, ranging from a few watts to megawatts. In order to generate high power in terms of megawatts ranges, the power electronics converters play a major role. In this, multilevel inverters (MLIs) are predominant power converters which are highly suitable for medium and high voltage applications like high power AC drives, FACTS devices, HVDC transmission, and large-scale wind and photovoltaic systems1,2. Compared to the traditional two-level inverter, the MLIs have low voltage stress on power devices, low electromagnetic interference, low total harmonic distortion (THD), reduced common-mode voltage, and enhanced output voltage (Vout)3,4. The first MLI reported in 1975 is by Baker and was named as cascaded H-bridge inverter (CHB). Next, both neutral point clamp (NPC) and flying capacitor, referred to as a floating capacitor (FC) topology were introduced in 1980–1981 by A. Nabae.

Generally speaking, the conventional MLI topologies have been known for their good modularity and low voltage stress on switches. Nevertheless, they have a higher number of switching devices, clamping diodes, isolated dc sources, and bulky dc-link capacitors5. In addition, they are only suitable for constant isolated dc source. In other words, the conventional MLIs are not suitable for photovoltaic (PV) applications since the output voltage of PV fluctuates due to the uncertainty of the solar irradiance and temperature. Further, the output voltage of PV is relatively low, in which the dc/dc boost converter is used on the front side of the inverter to regulate and boost the PV output voltage. However, as the output voltage is boosted at a higher level than the desired, the input voltage (Vin) is boosted to match the load requirement, which gives more burden in terms of high voltage stress and high value of the magnetic component to the front-end dc/dc converter. To reduce the front-end dc/dc converter voltage rating, a various switched capacitor MLI is proposed with voltage gain not less than one. In particular, the neutral point-based topologies need a higher input voltage, which can be rectified using the boost type inverter.

The combination of conventional topologies and other recently developed topologies forms the so-called hybrid MLI.

For example, the active neutral point clamped (ANPC) inverter topology is widely used for induction motor drive or AC grid-connected applications. The output voltage of the ANPC topology is half of the input voltage, and hence, it needs a high dc-link capacitor. Among the various hybrid ANPC topologies, the combination of ANPC and FC has gained more attention due to a single dc source generating a higher number of voltage levels. The switched capacitor MLI (SCMLI) topologies, which are capable of generating a 9L output voltage waveform, are widely presented in6,7,8,9,10,11,12,13,14. A new switched capacitor topology without the capacitor voltage sensor is proposed in6. Voltage balancing of the capacitors is achieved using a logic function, and it is embedded into a pulse decoder. In7, both the high and low voltage switches are operated by low and high switching frequencies, respectively, to reduce the power losses, and the capacitors are naturally balanced. A 9L double hybrid active NPC inverter topology presented in8 employs digital logic functions to balance capacitor voltage with the help of a voltage sensor. However, these topologies output voltage is equal to the input voltage.

To resolve the above problems, SCMLIs with boosting ability topologies are introduced in9,10,11,12,13,14. In9, a multicell structure with self-capacitor voltage balancing and boosting is presented. The full-bridge inverter circuit is used to produce an alternate output voltage waveform. However, the number of switches and voltage ratings of switches are considerably high. A new 9L quadratic boost converter topology with the self-voltage balancing is proposed in10,11. Nevertheless, it needs a capacitor and switches with a diversified voltage rating. Further, the voltage rating of the capacitor is higher than the input voltage, which limits its application to high voltage fields. A single-stage compact MLI with self-voltage balancing and boosting is presented in12,13,14. Here, the number of power components and blocking voltage on the switches are reduced. The voltage rating of the capacitor is half of the input voltage in12,13, but in14, the rating of the capacitor is equal to the input voltage. However, the previously mentioned topologies are not optimized concerning a lower number of power components or voltage stress on switches. Further, the voltage rating of the capacitor is also higher in a few topologies, which motivates this study to present a novel voltage boosting type topology with reduced switch count.

This paper successfully develops a 9L-ANPC topology to overcome the drawbacks of the existing topologies with low voltage rating components devised. The pertinent advantages of the proposed topology are

  1. (1)

    The conventional NPC and ANPC topologies output voltage is half of the input voltage, which is rectified, and the output voltage is boosted to be equal to the input voltage.

  2. (2)

    It does not require a sensor to measure the capacitor voltage.

  3. (3)

    In the front end, the low voltage dc/dc boost converters are required.

  4. (4)

    Due to less number of components, it features reduced power losses.

  5. (5)

    The capacitor voltages are independent of the load power factor.

  6. (6)

    The proposed modulation scheme offers low THD.

A detailed discussion about the proposed structure, modes of operation, loss calculation, and experimental validations are presented in the sequel.

Proposed 9L-ANPC inverter

The proposed 9L switched-capacitor inverter topology is shown in Fig. 1. It comprises an improved T-type inverter, auxiliary switch, and switched cell (SC) unit. The improved T-type inverter consists of two dc-link capacitors (C1, C2) connected in parallel with the input dc source (Vin), two unidirectional IGBT’s with anti-parallel diodes (S1, S1′), and one bidirectional switch (B1). The SC consists of two series-connected capacitors (Ca and Cb), four unidirectional IGBT’s with anti-parallel diodes (S2, S2′, S3, and S3′), and one bidirectional switch (B2). The Auxiliary switch (Sx) is used to discharge the capacitors Ca and Cb during positive and negative half-cycles. The input voltage is shared among the dc-link capacitors C1 and C2, in which VC1 = VC2 = Vin/2 and Vo = M × Vin (M-modulation index, Vo = Vout), balanced by the switch B1.

Figure 1
figure 1

Proposed single-phase basic unit for 9L operation.

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The capacitors C1 and C2 supply the dc voltage to the load during positive and negative half-cycle, respectively. The fundamental operation of proposed 9L inverter is given in Table 1.

Table 1 Fundamental operation of proposed 9L inverter.
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As shown in Fig. 2, the designated points of output A, O, and B are the node points used to calculate the RMS voltage. Initially, at point A, Vin/2 is present, i.e. (Vin/2 − 0), and the voltage difference between point O to A is Vin/2 − VCa = Vin/4. At this point, the switch B2 is turned on. At point B, the capacitors are charged to Vin/4 and the voltage, i.e., Vin/2 − VCa − VCb = 0 V. The current path for each voltage level and the corresponding switching sequence are given in Table 1, and for simple understanding, only the positive half-cycle and zero states are depicted in Fig. 2a–f. Mode 1 (+ Vin/4): In-state 1 and 2, the capacitors Ca, and Cb are charged to Vin/4 through switches S1, S2, S2′, D′ and B1, simultaneously the switch B2 is turned ON to produce output voltage equals to Vin/4, as given in Fig. 2a. Mode 2 (+ Vin/2): The capacitors Ca, and Cb charge through switches S1, S2, S2′, D′ and B1, simultaneously the switch S3 is turned ON to produce output voltage equals to Vin/2 as given in Fig. 2b. Mode 3 (+ 3Vin/4): States 3 and 4 discharge the capacitors Ca and Cb. To obtain + 3Vin/4 at the load, the capacitor C1 is connected to point B through auxiliary switch Sx. The load current (IL) flows through S1, Sx, S2′ and B1 to produce a third voltage level (+ 3Vin/4), as shown in Fig. 2c. Mode 4 (+ Vin): Both the switched cell capacitors are discharged through switches S1, Sx, S2′ and S3 as shown in Fig. 2d. Hence, the negative half-cycle is obtained by choosing the corresponding switching path. During state 3 (± 3Vin/4), capacitor Cb discharges during the positive half-cycle and Ca discharges during the negative half cycle. Mode 0 (0 V): The zero states are more essential to provide a freewheeling path to the load current when the load is inductive. The zero states are achieved either by turning on switches B1, S2, S3, D, D′ and Sx or B1, D, D′, Sx, S2′ and S3′ as shown in Fig. 2e,f. The proposed topology consists of two dc-link capacitors and two series-connected FCs. The FC voltages should be maintained to Vin/4, but the dc-link capacitor voltages are Vin/2. The output voltage (Vout) is obtained by using the switching functions, DC-link, and FC using Eq. (1):

$$V_{out} = \left( {S_{1} + S_{1}^{\prime } } \right)V_{in} - \left( {S_{2} - S_{2}^{\prime } } \right)V_{Cb} + \left[ {\left( {S_{3} - S_{3}^{\prime } } \right)S_{x} } \right]V_{Ca} - \left( {S_{x} + B_{1} } \right)\;\left( {D^{\prime } - D} \right)V_{Cb} {-}\left( {D^{\prime } - D} \right)V_{Ca} - B_{2} V_{Cb} - S_{1}^{\prime } V_{in} - S_{3}^{\prime } V_{Ca} - S_{x} \cdot S_{1}^{\prime } V_{C2} ,$$
(1)

where the VC2, VCa and VCb are the voltages of dc-link capacitor C2, floating capacitor Ca and Cb, respectively. The voltage across the dc-link capacitor and FCs are given in Eq. (2)

$$V_{C1} = V_{C2} = \frac{{V_{in} }}{2}, \, V_{Ca} = \, V_{Cb} = \frac{{V_{in} }}{4},$$
(2)
Figure 2
figure 2

Proposed ANPC 9L-BSCI operation (a–f) modes of operation of the positive half cycle.

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The {1,0} is the logic values of the switching function, i.e., the switch is ON state it represents as “1” and for OFF state represent as “0”, respectively. The corresponding switches are turned ON and OFF based on the given switching sequence in Table 2. The capacitance value of the FC depends on the ratio of charging and discharging time. Here, the FCs are charging and discharging is two times, but the duty cycle of charging is higher than the discharging, which means the proposed topology uses a lower number of dc capacitance. However, the current ratings are identical in all the switches. The maximum blocking voltage (MBV) on individual switches is obtained from Eqs. (3)–(5)

$$MBV_{S1,S2} = V_{in} ,$$
(3)
$$MBV_{S2,S2^{\prime}, \, S3,S3^{\prime},B1,Sx} = V_{in} /2,$$
(4)
$$MBV_{B2} = V_{in} /4,$$
(5)
Table 2 Switching sequence of each level.
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Total blocking voltage (TBV) is the sum of the blocking voltages on individual switches specified in per unit value, given in Eqs. (6)–(8).

$$TBV_{p \cdot u} = MBV_{S1,S1^{\prime}} + \, MBV_{S3,S3^{\prime},S2,S2^{\prime},B1,Sx} + \, MBV_{B2} ,$$
(6)
$$TBV_{p \cdot u} = 2V_{in} + 3V_{in} + 0.5V_{in} ,$$
(7)
$$TBV_{p \cdot u} = 5.5V_{in} .$$
(8)

Modified multicarrier triangular carrier signal

The conventional multicarrier PWM technique is used for low THD when the switching frequency is high. In order to reduce the switching frequency with reduced THD and high voltage RMS, a multicarrier level-shifted modulation scheme is introduced. The conventional carrier waveform under level-shifted multilevel pulse width modulation is decomposed into two intervals ranging from 0 to Ts/2 and Ts/2 to Ts with the amplitude of voltage varying from 0 to 1 and from 1 to 0 respectively in the mentioned time intervals as shown in Fig. 3a. To reduce the THDs and to increase the RMS value of the output voltage of the inverter, the proposed switching scheme under level-shifted multilevel pulse width modulation is subjected to a change in the amplitude of the carrier wave with the sampling time period of Ts equally divided into five intervals comprising of 0 to Ts/4, Ts/4 to Ts/2, Ts/2 to 3Ts/4 and 3Ts/4 to Ts. The amplitude in these intervals varies from 0 to 1, 1 to change in q (dq), dq to 1, and from 1 to 0, respectively, as illustrated in Fig. 3b. When dq = 0, the proposed scheme takes the shape of the conventional carrier waveform. When dq = 1, the proposed scheme modifies into the shape of an isosceles trapezoid. When dq = 1, a single pulse is generated in the time interval of Ts. This can further deteriorate the THD. Therefore, to mitigate this detrimental effect on THD, choosing the value of dq is of great significance. Figure 3c clearly shows the difference between the pulse width duration of the proposed carrier signal and the conventional triangular carrier signal.

Figure 3
figure 3

Proposed new carrier signal waveform (a) compared with conventional triangular waveform (b) with various dq points (c) comparison of proposed and triangular carrier signal with different pulse width variations.

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The optimal value of dq is chosen to be greater than 0 and lesser than 1. The generalized level-shifted carrier signal (Vcarr) with sinusoidal reference signal (VRef) is represented in Fig. 4a and the typical 9L output voltage waveform is shown in Fig. 4b. The Eq. (9) gives the function f(x,y) of two level full bridge inverter is

$$f(x,y) = \frac{{A_{00} }}{2} + \sum\nolimits_{{{\text{n}} = 1}}^{\infty } {\left[ {A_{0n} \cos ny + {\text{B}}_{0n} \sin ny} \right]} + \sum\nolimits_{{{\text{m}} = 1}}^{\infty } {\left[ {A_{0m} \cos my + {\text{B}}_{0m} \sin my} \right]} + \sum\nolimits_{m = 1}^{\infty } {\sum\nolimits_{{{\text{m}} = - \infty }}^{\infty } {\left[ {A_{mn} \cos (mx + ny) + {\text{B}}_{mn} \sin (mx + ny)} \right]\quad (n \ne 0),} }$$
(9)

where m is the carrier index variable and n is the baseband index variable. The above equation consists of the fundamental component, and harmonics15. Since the proposed topology produces the double pulse when dq ≠ 1, and the Fourier equation can be further reduced and given in Eq. (10)

$$A_{00} + jB_{00} = \frac{{2V_{in} }}{{2\pi^{2} }} \times \int\limits_{ - \pi }^{\pi } {\left( {1 + \pi M\cos y} \right) \, dy} ,$$
(10)

where ‘M’ is modulation index. Since, the duty ratio of the proposed modulation scheme is higher than the conventional PWM, the proposed topology conduction time is high. Further as the switching angle of each pulses is different from that of the conventional PWM, leads to reduction of THD in proposed PWM technique as shown in Fig. 3c.

Figure 4
figure 4

(a) Proposed multicarrier signal. (b) Typical 9L output voltage waveform.

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Determination of floating capacitors

The long discharging cycle (LDC) occurs for both the FCs during time interval (θ3 − (π − θ3)). The maximum charge, required by the capacitor is given in (11) where, iL represents the load current. As θ3 is obtained as in (12). Similarly, θ4 can be obtained.

$$\Delta Q = \int\limits_{{\theta_{3} }}^{{\pi - \theta_{3} }} {\frac{{i_{L} }}{\omega }} \, d\omega t,$$
(11)
$$\theta_{3} = \frac{{\sin^{ - 1} \left( {{\raise0.7ex\hbox{${3V_{carr} }$} \!\mathord{\left/ {\vphantom {{3V_{carr} } {V_{ref} }}}\right.\kern-\nulldelimiterspace} \!\lower0.7ex\hbox{${V_{ref} }$}}} \right)}}{{2\pi f_{f} }}.$$
(12)

The maximum voltage ripple occurred at the resistive load. So, it is worth mentioning that the maximum discharge value for pure resistive load. Therefore, the ΔQ can be calculated as in (9) for capacitor Ca and Cb.

$$\Delta Q_{C1} = \frac{{v_{in} }}{{2\pi f_{f} R_{L} }} \, \left( {(\pi - \theta_{3} ) - \theta_{3} } \right).$$
(13)

The ripple value (ΔVrip) across the capacitor Ca and Cb is obtained (11) as RL is the resistive load and ff is the inverter output voltage frequency. The optimum value for each capacitor (Copt) can be given as in (12).

$$\Delta V_{rip} = \frac{{v_{in} }}{{2\pi f_{f} R_{L} C}} \times (\pi - 2\theta_{3} ),$$
(14)
$$C_{opt} = \frac{{v_{in} }}{{2\pi f_{f} R_{L} \Delta V_{rip} }} \times \left( {\pi - 2\theta_{3} } \right).$$
(15)

Comparison of proposed multilevel inverter with other recent MLI topologies

A comparison of different switched capacitor MLI topology and conventional topologies are considered. In order to generate the 9L output voltage at the load, the CHB, NPC, and FC topologies use 16 switches; other than these, the NPC and FC need more clamping diodes, clamping capacitors, and additional dc-link balancing circuits. However, in the case of CHB, it needs four isolated dc sources and no voltage boosting. Apart from the conventional topologies,10 developed a topology where eight switches and three diodes are used, but it requires four maximum blocking voltage (MBV) switches. The ratio of the input voltage versus the maximum blocking voltage is 1:4 (Vin: MBV). Although the topologies in6,8 are close to the proposed topology with the total standing voltage of 6 Vin, these topologies do not have voltage boosting ability, unlike the proposed topology. The other parameters such as voltage rating of the capacitor (VC,rating), the number of the capacitors (NCapacitors), number of the diodes (Ndiode) and number of sources (Nsource) are compared and presented in Table 3 with recent 9L SCMLI topologies. Further, the recent topologies presented in16,17 are compared with the proposed topology. In16, the topology does not have boosting ability and it is not an NPC type topology but the17 is family of ANPC with high voltage gain with more number of switches. Further, the maximum blocking voltage is equal to the Vout. However, from the Table 3, its confirming that the proposed topology is superior to the all-other topologies presented in the literature in terms of switch count.

Table 3 Comparison of proposed 9L-inverter with conventional and other recent SCMLI topologies.
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Power loss analysis of the proposed topology

The losses in the power components occur due to non-idealities present with them. Three components compose the multilevel ANPC inverters’ power losses are the switching losses, conduction losses of the power semiconductor devices, and ripple losses of the capacitors.

$$P_{loss} = P_{c} + P_{sw} + {\text{P}}_{ripple} ,$$
(16)

where Ploss denotes the total power loss of the MLI with Pc, Psw, and Pripple represents the switches losses, conduction losses and ripple losses, respectively. As a consequence of intrinsic delays in the switching of semiconductor components, during each switching transition overlaps between voltage and current leading to loss of switching which is calculated as

$$P_{sw} = \left[ {\sum\limits_{switches}^{{}} {\,\,\,\sum\limits_{{within\,\,{\raise0.7ex\hbox{$1$} \!\mathord{\left/ {\vphantom {1 {f_{o} }}}\right.\kern-\nulldelimiterspace} \!\lower0.7ex\hbox{${f_{o} }$}}}}^{{}} {\left( {\frac{{V_{on} \times I_{on} \times T_{on} }}{6} + \frac{{V_{off} \times I_{off} \times T_{off} }}{6}} \right)} } } \right] \times f_{f} ,$$
(17)

where, Von is pre-ON state voltage across the power switch. Ion is the current which flows through the power switch after the ON condition. Ton is the period of transition in the ON state. Voff, Ioff, and Toff are the voltage across the power switch, current that flows through a power switch before the transition to OFF state and transition period of the OFF state, respectively. ff is the frequency of the fundamental output voltage. Conduction losses are power losses occurred due to the internal resistance offered by the switch during the conduction mode and is given as

$$P_{c} = \sum\limits_{all\,\,switches} {I_{sw}^{2} \times R_{on} } ,$$
(18)

where Isw is the amount of current through a switch with an internal resistance of Ron.

Aside from power losses in the switch, the ripple losses, which occur due to the charging and discharge of the capacitors, are another major contributor to the overall power loss of the MLI. When the parallel capacitor to the dc source is charged, the charging current flows through the capacitor, and because of the difference in voltage between the input source and the capacitor voltage, the ripple voltage ΔVC causes the power loss. The ripple power loss of a capacitor can be calculated as

$$P_{ripple} = \sum\limits_{all\,\,capacitors} {C \times \Delta V_{C} \times f_{f} } .$$
(19)

Modeling the semiconductor devices in PLECS software has led to the power load distribution for the proposed topology. The efficiency of the proposed topology against the output power has been shown in Fig. 5. The proposed topology’s maximum efficiency was measured at 200 W output power as 97.7%. The efficiency of the proposed topology is 94.1% at the output power of 2 kW. Even with higher output power, the proposed topology gives better efficiency, making it suitable for higher power applications.

Figure 5
figure 5

Efficiency curves of the proposed topology.

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Table 4 shows the power loss of all switches and capacitors, together with the efficiency of the proposed topology with different loading combinations. Table 4 also shows the switching power loss (Psw) and conduction power loss (Pc) of the devices with a ripple power loss of the capacitors. The maximum power loss occurs to the switch pair (S2, S2′) as these switches have to carry the charging current of the capacitors Ca and Cb. During charging the FCs, the charging current will be higher, leading to major losses in the devices and components. In Fig. 6, the dc-link capacitors have low power loss, but the FC losses are high (~ 16%), and the diodes presented in the mid-point of the dc-link capacitor also produce more losses because of the FC charging current. The bidirectional switch (B1) can be replaced with two switches that may reduce the losses and increase efficiency. Nevertheless, the switch count and driver circuit will be added extra, leading to an increase in the inverter’s cost. The sources of losses are switching the device and conduction loss during the ON time which is clearly cleared discussed in above section. Further, the other losses are: (i) DC link capacitor losses: These losses are mostly associate with capacitor voltage ripple and ESR value of the capacitors. Here, the ESR value of the capacitor is fixed by the manufacturer. (ii) Floating capacitor losses: The FC losses are high due to high charging current flowing in the charging loop. So, the FC capacitor leads to higher losses. However, in all the self-balanced switched capacitor topologies experiencing this loss.

Table 4 Power loss distribution of the proposed topology.
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Figure 6
figure 6

Power loss distribution.

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The voltage and current across each switch for one switching period is given in Fig. 7a,b. It is confirming that the maximum blocking voltage on switch is equal to the Vin and the maximum current has occurred on the charging path devices.

Figure 7
figure 7

One cycle switching period waveform (a) for voltage and (b) for current.

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Experimental results

The performance of the proposed 9L inverter is tested and verified in prototype hardware setup. The circuit diagram of proposed 9L inverter with PV applications for single and three phase system is shown in Fig. 8a,b. In hardware, the Xilinx Spartan 6 digital controller is used. The list of experimental parameters values is given in Table 5. In this Vin is chosen as 200 V and output voltage is 200 V with unity gain. C1 and C2 capacitors are chosen as 1700 µF with low voltage ripple of 2% but in switched cell capacitors values are selected as 2700 µF based on the ripple voltage and switching frequency of the inverter as given in Eq. (15) and ΔVC is the ripple voltage of capacitor Ca and Cb, which range between 0.05 to 0.1 i.e., 5% to 10% variation and the fsw is switching frequency. The recommended modulation scheme is verified in experiments for a switching frequency of 2.5 kHz. Further to validate the proposed system for real-time applications, the prototype hardware model is fabricated. In hardware setup, the Semikron SKM75GB063D IGBT 600 V/75 A and TLP-250A gate driver circuits are used. The dead time of 4 µs is provided by using RC network. RL load is varied in the order of low–high-low to measure the adaptability of proposed inverter with respect to dynamic behavior and modulation under sudden load conditions as shown in Fig. 9a–g. In Fig. 9a the output voltage (M = 0.95 to 1.0) and current waveform for 10 Ω + 100 mH is presented with worst case of power factor is 0.3 and the simultaneously the dc-link capacitor and FC voltages are presented in Fig. 9b. Further, the load changes from 100 Ω, 50 mH to 10 Ω, 100 mH to confirm the suitability of proposed topology for any load variations as presented in Fig. 9c and load to no-load is shown in Fig. 9d. However, the load variations are limited based on the FC value. The maximum current through the switch is 6.0 A and the maximum blocking voltage is 200 V on S1 and S1′ switches.

Figure 8
figure 8

Circuit diagram of proposed 9L ANPC Topology for (a) single phase system and (b) three phase system.

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Table 5 System parameter values.
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Figure 9
figure 9

various experimental results of proposed 9L ANPC topology (a) output voltage and current for 10 Ω, 100 mH, (b) FC and dc-link capacitor voltages, (c) load changes from 100 Ω, 50 mH to 10 Ω, 100 mH, (d) load changes from 10 Ω, 100 mH to disconnected loads, (e) modulation index variation from 0.8 to 1.0, (f) the step input voltage changes from 100 to 200 V, (g) voltage and current of switch S3/S3′ and (h) floating capacitor currents during step input voltage changes.

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Another dynamic variation is modulation index changes from 0.8 to 1.0, and the Vin changes from 100 to 200 V, as shown in Fig. 9f. In switched capacitor topology, the inrush current is another problem during the parallel connection of FC and input dc source. Due to inrush current need high current rated switches. In order to suppress the inrush current, the inductor is used in the loop, see the switch current and voltage in Fig. 9g. Further, during the step input voltage changes the capacitors charging current is increasing suddenly and it reach to ~ 30A as shown in Fig. 9h. The experimental output power is 1210.7 W for high inductive load value and 380.4 W for highly resistive load with the efficiency of 94.4% and 97.7%, respectively. The proposed inverter operates less power loss and less costly due to the low number of power components and voltage rating on the switches. Further, the voltage THD of the proposed modulation scheme is compared with the conventional phase disposition (PD), phase opposite disposition (POD) and alternate POD, and parabola modulation scheme for different modulation index (M) as listed in Table 6. The proposed modulation scheme generates THD of 12.6% in experimental for switching frequency 2.5 kHz as shown in Fig. 10. The photograph of the experimental setup for the proposed topology is given Fig. 11. The details of each components and sensors are given in Table 7.

Table 6 THD comparison of various modulation techniques for switching frequency of 2.5 kHz.
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Figure 10
figure 10

Experimental voltage THD spectrum.

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Figure 11
figure 11

Prototype model of proposed 9L inverter.

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Table 7 Experimental components details and rating.
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Conclusion

In this paper, a 9L-ANPC type topology and its operation have been presented. The proposed topology gain is equal to the Vin, where 200 V is applied as input and 200 V is obtained at the output. The number of switch count is reduced with reduced FC voltage rating. The proposed topology is experimentally verified, and results are presented. The proposed topology is tested with a high inductive load value of 10 Ω/100 mH, which is approximately 0.3 power factor, and the proposed topology can generate the output voltage with 9L. Further, the loss values and power loss distribution for 100 Ω + 50 mH are presented, and 97.7% efficiency is achieved. The experimental results concluded that the proposed topology has self-voltage balancing and voltage boosting ability. Further, this topology is suitable for PV applications.