Skip to main content

Thank you for visiting nature.com. You are using a browser version with limited support for CSS. To obtain the best experience, we recommend you use a more up to date browser (or turn off compatibility mode in Internet Explorer). In the meantime, to ensure continued support, we are displaying the site without styles and JavaScript.

  • Review Article
  • Published:

Nanometre-scale electronics with III–V compound semiconductors

Nature volume 479, pages 317–323 (2011)Cite this article

Subjects

Abstract

For 50 years the exponential rise in the power of electronics has been fuelled by an increase in the density of silicon complementary metal–oxide–semiconductor (CMOS) transistors and improvements to their logic performance. But silicon transistor scaling is now reaching its limits, threatening to end the microelectronics revolution. Attention is turning to a family of materials that is well placed to address this problem: group III–V compound semiconductors. The outstanding electron transport properties of these materials might be central to the development of the first nanometre-scale logic transistors.

This is a preview of subscription content, access via your institution

Access options

Buy this article

  • Purchase on Springer Link
  • Instant access to full article PDF
Buy now

Prices may be subject to local taxes which are calculated during checkout

Figure 1: Electron and hole mobility of group III–V compound semiconductors.
Figure 2: Electron injection velocity in III–V HEMTs.
Figure 3: High 'on' currents in III–V HEMTs.
Figure 4: Possible future MOSFETs using a III–V compound semiconductor channel.

Similar content being viewed by others

References

  1. Ferain, I., Colinge, C. A. & Colinge, J.-P. Multigate transistors as the future of classical metal–oxide–semiconductor field-effect transistors. Nature 479, 310–316 (2011).

    Article  CAS  ADS  PubMed  Google Scholar 

  2. Chau, R., Doyle, B., Datta, S., Kavalieros, J. & Zhang, K. Integrated nanoelectronics for the future. Nature Mater. 6, 810–812 (2007).

    Article  CAS  ADS  Google Scholar 

  3. Iwai, H. Roadmap for 22 nm and beyond. Microelectron. Eng. 86, 1520–1528 (2009).

    Article  CAS  Google Scholar 

  4. Frank, D. J. Power-constrained CMOS scaling limits. IBM J. Res. Dev. 46, 235–244 (2002).

    Article  Google Scholar 

  5. Theis, T. N. & Solomon, P. M. In quest of the “next switch”: prospects for greatly reduced power dissipation in a successor to the silicon field-effect transistor. Proc. IEEE 98, 2005–2014 (2010).

    Article  Google Scholar 

  6. del Alamo, J. A. The high-electron mobility transistor at 30: impressive accomplishments and exciting prospects. Int. Conf. Compound Semicond. Manuf. Technol. 17–22 (CS ManTech, 2011).

    Google Scholar 

  7. ITRS, International Technology Working Groups International Technology Roadmap for Semiconductors 〈http://www.itrs.net/Links/2010ITRS/Home2010.htm〉 (ITRS, 2010).

  8. Kim, D.-H. et al. 50-nm E-mode In0.7Ga0.3As PHEMTs on 100-mm InP substrate with f max > 1 THz. IEEE Int. Electron Devices Meet. 692–695 (IEEE, 2010).

    Google Scholar 

  9. Kim, D.-H. & del Alamo, J. A. 30-nm InAs PHEMTs With f T = 644 GHz and f max = 681 GHz. IEEE Electron Device Lett. 31, 806–808 (2010).

    Article  CAS  ADS  Google Scholar 

  10. Leuther, A. et al. 20 nm Metamorphic HEMT with 660 GHz f T. Int. Conf. Indium Phosphide Relat. Mater. (IEEE, 2011).

    Google Scholar 

  11. Jeong, C., Antoniadis, D. A. & Lundstrom, M. S. On backscattering and mobility in nanoscale silicon MOSFETs. IEEE Trans. Electron Devices 56, 2762–2769 (2009).

    Article  CAS  ADS  Google Scholar 

  12. del Alamo, J. A., Kim, D.-H., Kim, T.-W., Jin, D. & Antoniadis, D. A. III–V CMOS: what have we learned from HEMTs? Int. Conf. Indium Phosphide Relat. Mater. (IEEE, 2011).

    Google Scholar 

  13. Kim, D. H., del Alamo, J. A., Antoniadis, D. A. & Brar, B. Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs. IEEE Int. Electron Devices Meet. 861–864 (IEEE, 2009). This paper reports that the electron injection velocity in InGaAs and InAs HEMTs is more than double that in Si MOSFETs of similar gate length at half the voltage.

    Google Scholar 

  14. Khakifirooz, A. & Antoniadis, D. A. MOSFET performance scaling — part I: historical trends. IEEE Trans. Electron Devices 55, 1391–1400 (2008).

    Article  CAS  ADS  Google Scholar 

  15. Liu, Y. et al. in Fundamentals of III–V Semiconductor MOSFETs (eds Oktyabrsky, S. & Ye, P. D.) 31–50 (Springer, 2010).

    Book  Google Scholar 

  16. Fischetti, M. V. & Laux, S. E. Are GaAs MOSFETs worth building? A model-based comparison of Si and GaAs n-MOSFETs. IEEE Int. Electron Devices Meet. 481–484 (IEEE, 1989).

    Google Scholar 

  17. Jin, D., Kim, D.-H., Kim, T. & del Alamo, J. A. Quantum capacitance in scaled down III–V FETs. IEEE Int. Electron Devices Meet. 495–498 (IEEE, 2009).

    Google Scholar 

  18. Kim, T.-W., Kim, D.-H. & del Alamo, J. A. Logic characteristics of 40 nm thin-channel InAs HEMTs. Int. Conf. Indium Phosphide Relat. Mater. 496–499 (IEEE, 2010).

    Google Scholar 

  19. Kim, T.-W. & del Alamo, J. A. Injection velocity in thin-channel InAs HEMTs. Int. Conf. Indium Phosphide Relat. Mater. (IEEE, 2011).

    Google Scholar 

  20. Kim, D.-H. & del Alamo, J. A. 30 nm E-mode InAs PHEMTs for THz and future logic applications. IEEE Int. Electron Devices Meet. 719–722 (IEEE, 2008).

    Google Scholar 

  21. Dewey, G. et al. Logic performance evaluation and transport physics of Schottky-gate III–V compound semiconductor quantum well field effect transistors for power supply voltages (V CC) ranging from 0.5 V to 1.0 V. IEEE Int. Electron Devices Meet. 487–490 (IEEE, 2009).

    Google Scholar 

  22. Umansky, V. et al. MBE growth of ultra-low disorder 2DEG with mobility exceeding 35 × 106 cm2/Vs. J. Cryst. Growth 311, 1658–1661 (2009).

    Article  CAS  ADS  Google Scholar 

  23. Spicer, W. E., Lindau, I., Skeath, P. & Su, C. Y. Unified defect model and beyond. J. Vac. Sci. Technol. 17, 1019–1027 (1980).

    Article  CAS  ADS  Google Scholar 

  24. Hinkle, C. L. et al. GaAs interfacial self-cleaning by atomic layer deposition. Appl. Phys. Lett. 92, 071901 (2008).

    Article  ADS  CAS  Google Scholar 

  25. Scarrozza, M. et al. A theoretical study of the initial oxidation of the GaAs(001)-β2(2×4) surface. Appl. Phys. Lett. 95, 253504 (2009).

    Article  ADS  CAS  Google Scholar 

  26. Becke, H., Hall, R. & White, J. Gallium arsenide MOS transistors. Solid State Electron. 8, 813–818 (1965).

    Article  CAS  ADS  Google Scholar 

  27. Mimura, T., Odani, K., Yokoyama, N., Nakayama, Y. & Fukuta, M. GaAs microwave MOSFETs. IEEE Trans. Electron Devices 25, 573–579 (1978).

    Article  ADS  Google Scholar 

  28. Passlack, M. et al. In-situ Ga203 process for GaAs inversion/accumulation device and surface passivation applications. IEEE Int. Electron Devices Meet. 383–386 (IEEE, 1995).

    Book  Google Scholar 

  29. Passlack, M., Hong, M. & Mannaerts, J. P. Quasistatic and high frequency capacitance–voltage characterization of Ga2O3–GaAs structures fabricated by in situ molecular beam epitaxy. Appl. Phys. Lett. 68, 1099–1101 (1996).

    Article  CAS  ADS  Google Scholar 

  30. Passlack, M., Hong, M., Mannaerts, J. P., Kwo, J. R. & Tu, L. W. Recombination velocity at oxide–GaAs interfaces fabricated by in situ molecular beam epitaxy. Appl. Phys. Lett. 68, 3605–3607 (IEEE, 1996).

    Article  CAS  ADS  Google Scholar 

  31. Ren, F. et al. Enhancement-mode p-channel GaAs MOSFETs on semi-insulating substrates. IEEE Int. Electron Devices Meet. 943–945 (IEEE, 1996).

    Google Scholar 

  32. Ren, F. et al. Demonstration of enhancement-mode p- and n-channel GaAs MOSFETS with Ga2O3(Gd2O3) As gate oxide. Solid State Electron. 41, 1751–1753 (1997).

    Article  CAS  ADS  Google Scholar 

  33. Ye, P. D. et al. GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition. IEEE Electron Device Lett. 24, 209–211 (2003).

    Article  CAS  ADS  Google Scholar 

  34. Frank, M. M. et al. HfO2 and Al2O3 gate dielectrics on GaAs grown by atomic layer deposition. Appl. Phys. Lett. 86, 152904 (2005).

    Article  ADS  CAS  Google Scholar 

  35. Huang, M. L. et al. Surface passivation of III–V compound semiconductors using atomic-layer-deposition-grown Al2O3 . Appl. Phys. Lett. 87, 252104 (2005).

    Article  ADS  CAS  Google Scholar 

  36. Milojevic, M. et al. Half-cycle atomic layer deposition reaction studies of Al2O3 on (NH4)2S passivated GaAs(100) surfaces. Appl. Phys. Lett. 93, 252905 (2008).

    Article  ADS  CAS  Google Scholar 

  37. Xuan, Y., Lin, H. C., Ye, P. D. & Wilk, G. D. Capacitance–voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric. Appl. Phys. Lett. 88, 263518 (2006).

    Article  ADS  CAS  Google Scholar 

  38. Li, N. et al. Properties of InAs metal-oxide-semiconductor structures with atomic-layer-deposited Al2O3 dielectric. Appl. Phys. Lett. 92, 143507 (2008).

    Article  ADS  CAS  Google Scholar 

  39. Wu, Y. Q., Xuan, Y., Ye, P. D., Cheng, Z. & Lochtefeld, A. Inversion-type enhancement-mode InP MOSFETs with ALD Al2O3, HfO2 and HfAlO nanolaminates as high-κ gate dielectrics. IEEE Device Res. Conf. 117–118 (IEEE, 2007).

    Google Scholar 

  40. Wang, W., Xiong, K., Wallace, R. M. & Cho, K. Impact of interfacial oxygen content on bonding, stability, band offsets, and interface states of GaAs:HfO2 interfaces. J. Phys. Chem. C 114, 22610–22618 (2010).

    Article  CAS  Google Scholar 

  41. Lin, L. & Robertson, J. Defect states at III–V semiconductor oxide interfaces. Appl. Phys. Lett. 98, 082903 (2011). This paper provides density-functional theory calculations of interface defect states between high- κ oxides and GaAs, InAs and InP that are consistent with experimental observation.

    Article  ADS  CAS  Google Scholar 

  42. Wang, W., Lee, G., Huang, M., Wallace, R. M. & Cho, K. First-principles study of GaAs(001)-β2(2×4) surface oxidation and passivation with H, Cl, S, F, and GaO. J. Appl. Phys. 107, 103720 (2010).

    Article  ADS  CAS  Google Scholar 

  43. Passlack, M., Droopad, R. & Brammertz, G. Suitability study of oxide/gallium arsenide interfaces for MOSFET applications. IEEE Trans. Electron Devices 57, 2944–2956 (2010). This experimental study of oxide–GaAs interfaces for MOSFET applications finds that whereas in situ -deposited Ga 2 O 3 leads to excellent interfacial quality, ex situ ALD-deposited Al 2 O 3 on GaAs leads to Fermi-level pinning.

    Article  CAS  ADS  Google Scholar 

  44. Trinh, H. D. et al. The influences of surface treatment and gas annealing conditions on the inversion behaviors of the atomic-layer-deposition Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitor. Appl. Phys. Lett. 97, 042903 (2010).

    Article  ADS  CAS  Google Scholar 

  45. O'Connor, E. et al. A systematic study of (NH4)2S passivation (22%, 10%, 5%, or 1%) on the interface properties of the Al2O3/In0.53Ga0.47As/InP system for n-type and p-type In0.53Ga0.47As epitaxial layers. J. Appl. Phys. 109, 024101 (2011).

    Article  ADS  CAS  Google Scholar 

  46. Ok, I. & Lee, J. C. in Fundamentals of III–V Semiconductor MOSFETs (eds Oktyabrsky, S. & Ye, P. D.) 307–348 (Springer, 2010).

    Book  Google Scholar 

  47. Wu, Y. D. et al. Engineering of threshold voltages in molecular beam epitaxy-grown Al2O3/Ga2O3(Gd2O3)/In0.2Ga0.8As. J. Vac. Sci. Technol. B 28, C3H10–C3H13 (2010).

    Article  CAS  Google Scholar 

  48. Cheng, C.-W., Apostolopoulos, G. & Fitzgerald, E. A. The effect of interface processing on the distribution of interfacial defect states and the C–V characteristics of III–V metal-oxide-semiconductor field effect transistors. J. Appl. Phys. 109, 023714 (2011).

    Article  ADS  CAS  Google Scholar 

  49. Chen, Y.-T. et al. Fluorinated HfO2 gate dielectric engineering on In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors. Appl. Phys. Lett. 96, 103506 (2010).

    Article  ADS  CAS  Google Scholar 

  50. Engel-Herbert, R., Hwang, Y., Cagnon, J. l. & Stemmer, S. Metal-oxide-semiconductor capacitors with ZrO2 dielectrics grown on In0.53Ga0.47As by chemical beam deposition. Appl. Phys. Lett. 95, 062908 (2009).

    Article  ADS  CAS  Google Scholar 

  51. Liu, Y., Xu, M., Heo, J., Ye, P. D. & Gordon, R. G. Heteroepitaxy of single-crystal LaLuO3 on GaAs(111)A by atomic layer deposition. Appl. Phys. Lett. 97, 162910 (2010).

    Article  ADS  CAS  Google Scholar 

  52. Xu, M. et al. New insight into Fermi-level unpinning on GaAs: impact of different surface orientations. IEEE Int. Electron Devices Meet. 865–868 (IEEE, 2009).

    Google Scholar 

  53. Ishii, H. et al. High electron mobility metal–insulator–semiconductor field-effect transistors fabricated on (111)-oriented InGaAs channels. Appl. Phys. Express 2, 121101 (2009).

    Article  ADS  CAS  Google Scholar 

  54. Wang, C., Xu, M., Colby, R., Stach, E. A. & Ye, P. D. “Zero” drain-current drift of inversion-mode NMOSFET on InP (111)A surface. IEEE Device Res. Conf. 93–94 (IEEE, 2011).

    Book  Google Scholar 

  55. Ye, P. D., Xuan, Y., Wu, Y. Q. & Xu, M. Inversion-mode InxGa1−xAs MOSFETs (x = 53, 65, 75) with atomic-layer-deposited high-κ dielectrics. ECS Trans. 19, 605–614 (2009). This paper reports significant improvements in ALD oxide InGaAs MOSFET transistor characteristics as the InAs mole fraction in the channel is increased.

    Article  CAS  Google Scholar 

  56. Sonnet, A. M. et al. On the calculation of effective electric field in In0.53Ga0.47As surface channel metal-oxide-semiconductor field-effect-transistors. Appl. Phys. Lett. 98, 193501 (2011).

    Article  ADS  CAS  Google Scholar 

  57. Sonnet, A. M. et al. Remote phonon and surface roughness limited universal electron mobility of In0.53Ga0.47As surface channel MOSFETs. Microelectron. Eng. 88, 1083–1086 (2011).

    Article  CAS  Google Scholar 

  58. Oktyabrsky, S. et al. Electron scattering in buried InGaAs/high-κ MOS channels. ECS Trans. 35, 385–395 (2011).

    Article  CAS  Google Scholar 

  59. Radosavljevic, M. et al. Advanced high-κ gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications. IEEE Int. Electron Devices Meet. 319–322 (IEEE, 2009). This paper reports the best logic performance of a III–V MOSFET so far, exceeding that of state-of-the-art silicon MOSFETs at 0.5 V.

    Google Scholar 

  60. Kuhn, K. J., Liu, M. Y. & Kennel, H. Technology options for 22 nm and beyond. Int. Workshop Junct. Technol. 1–6 (IEEE, 2010).

    Google Scholar 

  61. Waldron, N., Kim, D.-H. & del Alamo, J. A. A self-aligned InGaAs HEMT architecture for logic applications. IEEE Trans. Electron Devices 57, 297–304 (2010).

    Article  CAS  ADS  Google Scholar 

  62. Kim, T.-W., Kim, D.-H. & del Alamo, J. A. 60 nm Self-aligned-gate InGaAs HEMTs with record high-frequency characteristics. IEEE Int. Electron Devices Meet. 696–699 (IEEE, 2010).

    Google Scholar 

  63. Singisetti, U. et al. Ultralow resistance in situ ohmic contacts to InGaAs/InP. Appl. Phys. Lett. 93, 183502 (2008). This paper reports Mo/n+–InGaAs ohmic contacts with contact resistance comparable to state-of-the-art silicon technology.

    Article  ADS  CAS  Google Scholar 

  64. Chin, H.-C., Gong, X., Liu, X. & Yeo, Y. Lattice-mismatched In0.4Ga0.6As source/drain stressors with in situ doping for strained In0.53Ga0.47As channel n-MOSFETs. IEEE Electron Device Lett. 30, 805–807 (2009).

    Article  CAS  ADS  Google Scholar 

  65. Terao, R. et al. InP/InGaAs composite metal–oxide–semiconductor field-effect transistors with regrown source and Al2O3 gate dielectric exhibiting maximum drain current exceeding 1.3 mA/μm. Appl. Phys. Express 4, 054201 (2011). This paper reports that a 100-nm gate length InGaAs MOSFET with raised epitaxially grown source and drain regions has excellent electrical characteristics.

    Article  ADS  CAS  Google Scholar 

  66. Doyle, B. S. et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Device Lett. 24, 263–265 (2003).

    Article  CAS  ADS  Google Scholar 

  67. Wu, Y. Q., Xu, M., Wang, R. S., Koybasi, O. & Ye, P. D. High performance deep-submicron inversion-mode InGaAs MOSFETs with maximum G m exceeding 1.1 mS/μm: new HBr pretreatment and channel engineering. IEEE Int. Electron Devices Meet. 323–326 (IEEE, 2009).

    Google Scholar 

  68. Radosavljevic, M. et al. Non-planar, multi-gate InGaAs quantum well field effect transistors with high-κ gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications. IEEE Int. Electron Devices Meet. 126–129 (IEEE, 2010).

    Google Scholar 

  69. Pearton, S. J. & Norton, D. P. Dry etching of electronic oxides, polymers, and semiconductors. Plasma Process. Polym. 2, 16–37 (2005).

    Article  CAS  Google Scholar 

  70. Hashemi, P., Gomez, L., Canonico, M. & Hoyt, J. L. Electron transport in gate-all-around uniaxial tensile strained-Si nanowire n-MOSFETs. IEEE Int. Electron Devices Meet. 1–14 (IEEE, 2008).

    Google Scholar 

  71. Suk, S. D. et al. High performance 5nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability. IEEE Int. Electron Devices Meet. 717–720 (IEEE, 2005).

    Google Scholar 

  72. Do, Q. T., Blekker, K., Regolin, I., Prost, W. & Tegude, F. J. Single n-InAs nanowire MIS-field-effect transistor: experimental and simulation results. IEEE Int. Indium Phosphide Relat. Mater. 392–395 (IEEE, 2007).

    Google Scholar 

  73. Egard, M. et al. Vertical InAs nanowire wrap gate transistors with f t > 7 GHz and f max > 20 GHz. Nano Lett. 10, 809–812 (2010).

    Article  CAS  ADS  PubMed  Google Scholar 

  74. Hock, G., Hackbarth, T., Erben, U., Kohn, E. & Konig, U. High performance 0.25 μm p-type Ge/SiGe MODFETs. Electron. Lett. 34, 1888–1889 (1998).

    Article  CAS  Google Scholar 

  75. Bennett, B. R., Ancona, M. G., Boos, J. B. & Shanabrook, B. V. Mobility enhancement in strained p-InGaSb quantum wells. Appl. Phys. Lett. 91, 042104 (2007).

    Article  ADS  CAS  Google Scholar 

  76. Bennett, B., Ancona, M., Boos, J., Canedy, C. & Khan, S. Strained GaSb/AlAsSb quantum wells for p-channel field-effect transistors. J. Cryst. Growth 311, 47–53 (2008).

    Article  CAS  ADS  Google Scholar 

  77. Radosavljevic, M. et al. High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (V CC = 0.5 V) logic applications. IEEE Int. Electron Devices Meet. 1–4 (IEEE, 2008).

    Google Scholar 

  78. Kuhn, K. J., Murthy, A., Kotlyar, R. & Kuhn, M. Past, present and future: SiGe and CMOS transistor scaling. ECS Trans. 33, 3–17 (2010).

    Article  CAS  Google Scholar 

  79. Xia, L., Boos, J. B., Bennett, B. R., Ancona, M. G. & del Alamo, J. A. Hole mobility enhancement in In0.41Ga0.59Sb quantum-well field-effect transistors. Appl. Phys. Lett. 98, 053505 (2011).

    Article  ADS  CAS  Google Scholar 

  80. Xia, L. V. T., Oktyabrsky, S. & del Alamo, J. A. Mobility enhancement of two-dimensional hole Gas in an In0.24Ga0.76As quantum well by <110> uniaxial strain. Int. Symp. Compound Semicond. 2011 (IEEE, in the press).

    Google Scholar 

  81. Nainani, A. et al. Engineering of strained III–V heterostructures for high hole mobility. IEEE Int. Electron Devices Meet. 857–860 (IEEE, 2009).

    Google Scholar 

  82. Gomez, L., Chleirigh, C. N., Hashemi, P. & Hoyt, J. L. Enhanced hole mobility in high Ge content asymmetrically strained-SiGe p-MOSFETs. IEEE Electron Device Lett. 31, 782–784 (2010).

    Article  CAS  ADS  Google Scholar 

  83. Passlack, M. et al. Self-aligned GaAs p-channel enhancement mode MOS heterostructure field-effect transistor. IEEE Electron Device Lett. 23, 508–510 (2002).

    Article  CAS  ADS  Google Scholar 

  84. Nainani, A. et al. Development of high-κ dielectric for antimonides and a sub 350 °C III–V pMOSFET outperforming germanium. IEEE Int. Electron Devices Meet. 138–141 (IEEE, 2010). This paper describes p-type InGaSb MOSFETs with an ALD Al 2 O 3 gate dielectric and excellent characteristics.

    Google Scholar 

  85. Pillarisetty, R. et al. High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (V cc = 0.5 V) III–V CMOS architecture. IEEE Int. Electron Devices Meet. 150–153 (IEEE, 2010).

    Google Scholar 

  86. Nakwaski, W. Thermal conductivity of binary, ternary, and quaternary III–V compounds. J. Appl. Phys. 64, 159–166 (1988).

    Article  CAS  ADS  Google Scholar 

  87. Hudait, M. K. et al. Heterogeneous integration of enhancement mode In0.7Ga0.3As quantum well transistor on silicon substrate using thin (≤ 2 μm) composite buffer architecture for high-speed and low-voltage (0.5 V) logic applications. IEEE Int. Electron Devices Meet. 625–628 (2007).

  88. Tang, C. W., Li, H., Zhong, Z., Ng, K. L. & Lau, K. M. Hetero-epitaxy of III–V compounds lattice-matched to InP by MOCVD for device applications. IEEE Int. Conf. Indium Phosphide Relat. Mater. 136–139 (IEEE, 2009).

    Google Scholar 

  89. Yokoyama, M. et al. Extremely-thin-body InGaAs-on-insulator MOSFETs on Si fabricated by direct wafer bonding. IEEE Int. Electron Devices Meet. 46–49 (2010).

  90. Ko, H. et al. Ultrathin compound semiconductor on insulator layers for high-performance nanoscale transistors. Nature 468, 286–289 (2010). This paper reports on thin-channel InAs-on-insulator MOSFETs with excellent electrical characteristics fabricated on a silicon substrate by a layer-transfer process.

    Article  CAS  ADS  PubMed  Google Scholar 

  91. Fang, H. et al. Strain engineering of epitaxially transferred, ultrathin layers of III–V semiconductor on insulator. Appl. Phys. Lett. 98, 012111 (2011).

    Article  ADS  CAS  Google Scholar 

  92. Fiorenza, J. et al. Aspect ratio trapping: a unique technology for integrating Ge and III–Vs with silicon CMOS. ECS Trans. 33, 963–976 (2010).

    Article  CAS  Google Scholar 

  93. Wu, Y. Q. et al. Atomic-layer-deposited Al2O3/GaAs metal-oxide-semiconductor field-effect transistor on Si substrate using aspect ratio trapping technique. Appl. Phys. Lett. 93, 242106 (2008).

    Article  ADS  CAS  Google Scholar 

  94. Moore, G. E. Cramming more components onto integrated circuits. Electronics 38, 114–117 (1965).

    Google Scholar 

  95. Hutcheson, G. D. in Into the Nano Era: Moore's Law Beyond Planar Silicon CMOS (ed. Huff, H.) 11–38 (Springer, 2009).

    Book  Google Scholar 

Download references

Acknowledgements

I have enjoyed stimulating discussions with students, collaborators and colleagues. I am particularly thankful to D. Antoniadis, R. Chau, S. Datta, J. Hoyt, D. Jin, D.-H. Kim, T.-W. Kim, A. Kummel, J. Lin, M. Lundstrom, S. Oktyabrsky, M. Passlack, M. Radosavljevic, E. Vogel, N. Waldron, R. Wallace, L. Xia and P. Ye. Research on III–V CMOS transistors at my lab at MIT has been funded by the Materials, Structures and Devices FCRP Center and Intel Corporation.

Author information

Authors and Affiliations

  1. Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, 02139, Massachusetts, USA

    Jesús A. del Alamo

Authors
  1. Jesús A. del Alamo
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Jesús A. del Alamo.

Ethics declarations

Competing interests

The author declares no competing financial interests.

Additional information

Reprints and permissions information is available at http://www.nature.com/reprints.

Rights and permissions

Reprints and permissions

About this article

Cite this article

del Alamo, J. Nanometre-scale electronics with III–V compound semiconductors. Nature 479, 317–323 (2011). https://doi.org/10.1038/nature10677

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1038/nature10677

This article is cited by

Comments

By submitting a comment you agree to abide by our Terms and Community Guidelines. If you find something abusive or that does not comply with our terms or guidelines please flag it as inappropriate.

Search

Advanced search

Quick links

Nature Briefing

Sign up for the Nature Briefing newsletter — what matters in science, free to your inbox daily.

Get the most important science stories of the day, free in your inbox. Sign up for Nature Briefing