Design and analysis of an all-optical processor for modular arithmetic
Introduction
The future Internet will rely on optical routers without the need for any optoelectronic conversion. Although optical technologies are playing increasingly important roles in wide and local area networks, current optical network elements still offer limited functionality compared to their electronic counterparts. All-optical digital processing is an exciting area of research towards finding new ways to process and transmit information entirely in the optical domain [1], [2]. Optical technology has distinct advantages in the area of transmission of information, e.g. massive bandwidth, absence of electromagnetic interference, and low power consumption. However, its electronic counterpart has the edge in logical processing and switching primarily due to the absence of an equivalent all-optical static memory. Therefore, all-optical digital ‘time-of-flight’ processing based on bit-serial architecture has been proposed [3], [4]. The authors in Refs. [3], [4] have demonstrated by proof-of-principle a bit-serial architecture for all-optical computing based on electro-optical directional couplers. In recent years, there are reports of low-level all-optical logic gates mostly based on the nonlinearity of semiconductor optical amplifiers (SOA) [5], [6], [7], [8].
In this paper, we present an all-optical processor that is based on the interconnection of low-level logic gates that overall performs modular (or modulo) arithmetic:If A is a positive number and B is between 0 and N, one can think of B as the remainder of A when divided by N. One important application of modular arithmetic is in crytography.
This main scope of this paper is the logical design of an all-optical processor by interconnecting several low-level logic gates. The modulo-processor has potential application in all-optical packet header processing. The design is based on the bit-serial architecture [3], [4] and consists of SOA logic gates commonly known as TOADs [9] (or sometimes SLALOM [21]) as the main building blocks. The modulo-processor is designed and tested with our own computer-aided-design (CAD) simulator, which is similar to equivalent circuit simulators in the electrical domain like PSPICE. Therefore, the CAD simulator is highly efficient since the TOAD gates are based on an analytical model that includes longitudinal effects [19].
In Section 2, we discuss the basic design of the all-optical modulo-processor. In that section, we also present simulation results of the processor operating at a low bit-rate (1 Gb/s) in order to demonstrate the correct logical function. In Section 3, we discuss some issues related to practical implementations such as cross-gain modulation (XGM) and recovery rate of the semiconductor optical amplifier.
Section snippets
Logical design
A basic algorithm to solve Eq. (1) is by repeatedly subtracting the input A by the divisor N until the remainder (or modulo-answer) B is obtained (inset of Fig. 1). The remainder is defined as the smallest positive number after repeated subtractions. In order to keep track of the sign (±), the most significant bit (MSB) is initially set to ‘0’ so that an overflow could be detected when it becomes ‘1’. The processing can be done entirely in the optical domain and is made possible by using TOADs
Results and discussion
Our objective in Section 2 was to demonstrate the correct logical function of the modulo-processor. In a practical implementation, some further considerations must be taken into account to ensure correct all-optical computation. The TOAD gates must be able to differentiate between the low-energy data pulses and high-energy control pulses. This is achieved either by: (i) wavelength conversion; or (ii) polarization rotation. Therefore, this may require additional gates. A current difficulty,
Conclusion
We have presented a logical design of an all-optical processor that performs modular arithmetic. The design is based on a bit-serial architecture with semiconductor optical amplifier-based logic gates as the main components. The design was tested by a CAD simulator and simulation results showed correct logical operation of the processor. The modulo-processor has potential application in optical packet header processing.
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