Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

Highlights

• CLARO chip capable of single-photon counting with 5 ns peaking time.

• Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors.

• No significant performance degradation is observed after irradiation.

Abstract

The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10¹² 1 MeV ${\mathrm{n}}_{\mathit{eq}}/{\mathrm{cm}}^2$ and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10¹⁴ cm⁻² and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step.

Introduction

The CLARO-CMOS chip is an application specific integrated circuit (ASIC) designed for single-photon counting. The first prototype has been designed in 0.35 micron AMS CMOS technology [1], [2] and features four channels, each made of a charge amplifier with 3-bit settable gain, plus a comparator with a 5-bit settable threshold (Fig. 1). Extensive laboratory tests were done on the chip that was able to readout simulated single photon signals in 25 ns or less (full baseline recovery) with a power consumption of 0.7 mW per channel at low rate, increasing up to 1.9 mW at 10 MHz rate.

The LHCb experiment is preparing for an important upgrade to be achieved around the year 2018 [3], [4]. The plans are to reach luminosities up to 2×10³³ cm⁻² s⁻¹ (5 times higher than the current one), with a collision rate of 40 MHz. In order to overcome the current limitation of ~1 MHz actual level zero trigger rate and reach 40 MHz continuous data taking, a substantial change in LHCb trigger and read-out architecture is needed. In addition all hybrid photo-detectors of the RICH [5], which contain an electronic adapted to the previous conditions, will be replaced by commercial Multi-anode PMTs (Ma-PMT), using a new external front-end electronics based on the CLARO-CMOS chip. The LHCb Collaboration has recently decided to adopt the CLARO-CMOS chip as the baseline option for the front-end electronics of the upgraded RICH detectors.