Deep n-well MAPS in a 130 nm CMOS technology: Beam test results
Introduction
Monolithic active pixel sensors (MAPS), with full in-pixel signal processing chain and sparsified readout, have the potential to fulfill the stringent requirements in terms of position resolution, readout speed and material budget for future experiments such as the SuperB Factory [1], [2] or the International Linear Collider. The innovative chip design that we adopted exploits the triple well option of the CMOS process for the collecting electrode. In this new approach, described in greater detail in [3], the signal processing chain for capacitive detectors and data sparsification is implemented at the pixel level, improving readout speed potential. The front-end stage is physically overlapped with the area of the sensitive element. The voltage gain is determined by the feedback capacitance of the charge preamplifier and the size of the collecting electrode can be up to about in a pixel cell with a pitch. Thus it is possible to include in the pixel cell some small competitive n-well regions, crucial to develop the logic for the sparsified readout. Competitive n-well regions could subtract charge from the main collecting n-well electrode causing an efficiency loss. In order to reduce this effect we kept the fill factor of the sensor at the level of 90%. In this paper we report on the beam test results for APSEL4D chip, a 4096 pixel matrix (32 rows and 128 columns), developed within the SLIM5 experiment [4].
Section snippets
APSEL4D chip
The APSEL4D chip consists of a 4096 pixel matrix with data driven readout architecture. The elementary cell of area includes a collecting electrode, featuring a buried deep n-type layer, and the full readout chain for signal processing [5]. The processing chain consists of a charge preamplifier with charge to voltage conversion independent of the detector capacitance, a shaping stage featuring a 200 or 400 ns peaking time and finally a discriminator used to compare the signal with a
Experimental setup for beam test
For the beam test we used 12 GeV/c momentum protons, delivered in spills of about 480 ms with 104–106 particles/spill. A reference telescope, composed of four double-sided silicon strip detectors with readout pitch and 2×2 cm2 area, was used for track reconstruction. The device under test (DUT) was placed on a motorized table with remote control inside the tracking volume, with two telescope detectors (TD) placed upstream and the other two downstream the DUT, respectively. The distance
Data analysis
The reconstruction of tracks is based on the hit information of the reference telescope. By combining adjacent fired strips we reconstruct the clusters for each TD for the U (horizontal) and the V (vertical) side. For each event we search for candidate tracks among all possible combinations of space points (SP), defined as pairs of U and V clusters, requiring one SP from each TD. We retain events with only one reconstructed track, after having applied a cut on the track probability. A
Conclusions
We presented the beam test results for the APSEL4D chip, a 4096 pixel matrix of pixel cell pitch, with custom readout architecture capable of performing data sparsification at pixel level. By using 12 GeV/c protons at the CERN PS accelerator, we measured a maximum hit efficiency exceeding 90% and an intrinsic hit resolution of about for both the 100 and the thickness prototypes. We measured a uniform hit efficiency across the matrix. The sensor inefficiency is partly due to the
Acknowledgments
This work was supported by the Italian Ministry for Education, University and Research and the Istituto Nazionale di Fisica Nucleare.
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Now at Laboratoire de Physique Nucleaire et de Hautes Energies, IN2P3/CNRS, F-75252 Paris, France.