Embedded void approach effects on intrinsic stresses in laterally grown GaN-on-Si substrate
Graphical abstract
Introduction
Gallium Nitride (GaN) offers superior performance for high frequency and high power electronic devices owing to its desired material properties such as high electric breakdown field, high electron saturation velocity and high mobility [1]. Additionally, it offers better properties for wireless applications by operating at high bias voltage, current densities, higher breakdown field resulting in higher microwave power density and consequently higher watts per unit input and output capacitance [2]. Likewise, GaN based materials showed diverse properties for solid state lighting applications including wide direct band gap, high chemical and thermal stability, and high mobility, making them convenient for efficiency LEDs and power electronics [3], [4], [5], [6], [7].
Though, lateral heterojunctions AlGaN/GaN grown on Silicon (Si) substrate is the principle platform towards commercial GaN power electronic devices. GaN-on-Si technology offers further cost effective and commercialized technology because of the low cost and matured technology of silicon substrates. Moreover, prompt progress in the epitaxial (EPI) growth, device design, packing technology, gate driving techniques and processing technology resulted in commercialized GaN on SI heterojunction power devices that is used to implement power converters with remarkable efficiency and compact size [1], [8].
Kutana et al. showed that the highest quality of GaN is attained in Wurtzite GaN c-plane (0 0 0 1) orientation by growing GaN on (1 1 1) silicon surface. The growth of c-plane film results in large internal electric field leading to low optoelectronic applications’ efficiency due to the nature of GaN as a polar material. Although non-polar GaN film offers a solution for this problem, it results in high density of stacking faults and threading dislocations. This structure presents integrated optoelectronic advantage of GaN along with commercial benefits of Si substrate [9].
Though, GaN/Si offers great advantage for several applications, it suffers from high density of dislocations that deteriorates its performance. Dislocations in GaN crystal encompasses residual stresses resulted from misfits in both lattice parameters and coefficient of thermal expansion between both materials. Such defects result in high leakage currents, non-radiative recombination sites and scattering centers leading to deteriorated electrical and optical properties [10], [11], [12], [13], [14], [15].
To enhance GaN based device performance and reliability, it’s vital to minimize the dislocation density in the GaN thin-film. Several researches have been conducted to minimize dislocation-densities in laterally grown GaN-on-Si for better device’s performance. Such techniques comprise of lateral over growth on SiO2 masks [16], [17], [18], [19], [20], [21], [22], [23], [24], Pendo Epiaxy [25], AIN interlayers [26], [27], [28], [29], growing SixN1-x layers [30], [31], [32], [33], [34] before GaN layer, SiH4 etching [35], [36] and nitride nano columns overgrowth [37]. Lately Bedair et al. [38], [39], [40] presented the embedded voids approach (EVA), which relies on the generation of micro-voids to reduce dislocation-density uniformly over a large area of the thin-film surface. These voids offer free surfaces for dislocations termination. The results of the analysis showed that EVA results in uniform reduction in the dislocation density by approximately two orders of magnitude. EVA is experimentally performed at three different steps starting with growth of thin films by the Metal Organic Chemical Vapor Deposition Technique (MOVDT), followed by surface etching using mask-less Inductively Coupled Plasma-Reactive Ion Etching (ICPRIE) technique to create voids near the interface followed by regrowth again of the thin film layer.
In the current study, a three-dimensional multiple-slip crystal plasticity based model and specialized finite-element formulations are used to address Wurtzite GaN growth on Si substrates. The formulation is based on accounting of thermal and intrinsic stresses as a result of different processing conditions and device structures. Commercial FE solver (ABAQUS) is used along with Düsseldorf Advanced Materials Simulation Kit (DAMASK) [15], [16] to model elastic and plastic behavior of GaN growth on Si substrate, both with/without embedded voids. It is found that EVA considerable reduces the interface stresses leading to low stress at the thin film layer.
This paper is organized as follows: the crystalline plasticity formulation is given in Section 2, the GaN-on-Si model is represented and validated in Section 3, the results are given in Section 4, and a summary and conclusion of the results is discussed in Section 5.
Section snippets
Crystal plasticity constitutive model
The crystal plasticity constitutive model utilized in the current study is based on the classical CPFEM formulations given by [41], [42], [43], [44], [45], [46], [47], [48], [49].
The deformation gradient is decomposed into elastic and inelastic parts:where, is the deformation rate tensor, and is the spin tensor or vorticity tensor:
The total deformation-rate tensor, , and the total spin tensor, , are similarly decomposed into elastic and plastic parts
GaN-on-Si model representation with EVA
A three-dimensional multiple-slip crystal plasticity model and specialized finite-element formulations were used to address Wurtzite GaN growth on Si substrate. The selection of cryptographic orientation is significant for the growth quality.
In wurtzite GaN the fundamental slip systems are and basal and prismatic systems respectively. Under high loading conditions, slipping activities are observed on the pyramidal systems. Since dislocations are observed only on basal and
EVA approach
In order to investigate the effect of EVA approach on intrinsic stresses in GaN/Si cell, a sub micro-void in the form of ellipsoid with different volume and aspect ratios has been introduced to the cell. Fig. 3 shows the result for 1% volume ratio and 3:1:1 aspect ratio at mid-section. Introducing the embedded void at the interface resulted in reduction in the top surface stresses from 751 to 653 (13% reduction) as shown in Fig. 3. In addition, noticeable reduction along the void side attained
Summary & conclusion
The current study is concerned with examining the effect of EVA, which is implemented to overcome thermal expansion coefficient and lattice mismatches on GaN-on-Si structure. Numerical simulations were conducted to investigate the targeted approach; the computational analysis encompasses addressing GaN thin-film growth on Si substrate using three-dimensional multiple-slip crystal plasticity model and specialized finite-element formulations.
Various volume and aspect ratios of micro-size embedded
Acknowledgments
Support from the British University in Egypt Young Investigators Research Grant (YIRG05) and JESOR Research Grant from the Academy of Scientific Research & Technology (ASRT) are greatly appreciated.
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