Design exploration of majority voter architectures based on the signal probability for TMR strategy optimization in space applications

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Abstract

Hardware redundancy is a well-known fault tolerance technique used in safety- and mission-critical systems. However, the hardening efficiency of such techniques relies on the robustness of the majority voter circuitry. This summary provides the design exploration of majority voter architectures to be used in radiation environments such as in space missions. An application-specific Single-Event Transient (SET) characterization based on the signal probability is proposed to optimize the Triple-Modular Redundancy (TMR) block insertion methodologies. Results show that the SET cross-section of complex-gate architectures presents low input dependence while for the NOR/NAND based architectures a higher dependence is observed due to the logical masking effects. Additionally, different from the other architectures, the NAND voter has shown a reduction in the SET rate as the signal probability is increased. Considering the signal probability p = 0.1, p = 0.5 and p = 0.9, the best design for the two analyzed orbits is the NOR, CMOS1 and NAND voter, respectively.

Introduction

Fault tolerance is increasingly necessary for advanced technology circuits due to the high complexity and susceptibility to physical defects and environment disturbances as provoked by radiation interactions [[1], [2], [3], [4]]. Safety- and mission-critical systems, such as satellites and aircraft flight control systems, are the primary applications using fault-tolerance techniques to improve reliability. A system is assumed to be fault-tolerant when its functionality is preserved even with the presence of faults. Commonly, redundancy is the core foundation of fault tolerance techniques proposed in the literature [3]. There is a variety of approaches, according to the redundant part added to the system, ranging from hardware and software to information and time redundancy [1]. Hardware redundancy, also known as spatial redundancy, is widely used in space applications due to its capability of performing fault detection and/or fault correction [2]. One of the most used technique is the so-called Triple-Modular Redundancy (TMR), in which the selected critical component or electronic circuit is triplicated and their outputs are connected to a majority voter (MJV) architecture, as shown in Fig. 1 [3]. Therefore, whenever two copies of the component are fault-free, the output of the majority voter will be also fault-free. However, if a fault occurs in the MJV, the technique fails to provide a correct function of the system.

The applicability of TMR schemes as a Radiation-Hardening-by-Design (RHBD) approach can extend from masking the effects of Single-Event Transients (SETs) in data paths or Single-Event Upsets (SEUs) in memory elements. However, the majority voter robustness against radiation effects is crucial for the fault detection and correction efficiency of TMR strategies. Few works in the literature have provided design studies on the radiation robustness of majority voters in terms of power, delay, area and SET cross-section [[5], [6], [7], [8]]. The work developed in [5] provides heavy-ion experimental data and proposes a relative efficiency criterion for the majority voter selection according to the TMR strategy. Two FinFET-based majority voter circuits were evaluated under the atmospheric environment in [7]. In this case, the NAND- and NOR-based voter circuits have shown a similar soft-error rate (SER) due to the symmetric sizing of the PFET and NFET devices provided by the strain engineering and width quantization at FinFET technology [7]. The work in [8] adopts a layout-level analysis through stick diagram to evaluate the diffusion area of majority voters and to calculate a fault masking ratio. Despite the layout-based approach, charge sharing between internal nodes and very importantly the intra-cell charge sharing effect in the multi-level circuit implementations are not considered, which can considerably increase the voter sensitivity or reduce it through pulse quenching effect [9]. Although the good fault coverage in TMR schemes, one of the main drawbacks of adopting redundancy-based hardening techniques is the considerably high increase in area and power consumption [[1], [2], [3]]. Thus, it is of utmost importance to adopt optimization strategies in the TMR block insertion to selectively address the most sensitive nodes in the target design and lower the impact on the area usage and power consumption.

In this work, a design exploration of majority voter architecture robust to SET effects is presented considering the SET cross-section dependence on the input signals. A Monte Carlo based prediction methodology is used along with the physical design information of each circuit to assess its sensitivity to high-energetic particle interactions. A deeper analysis of the input dependence of the circuit sensitivity is provided. Therefore, the main contribution of this work lays on: the characterization of the input dependence of the SET cross-section in different majority voter architectures; and, the proposal of adopting signal probability analysis to provide an application-specific SET assessment of the designs and, consequently, to optimize the TMR insertion strategies in fault-tolerant systems for space applications.

This paper is organized as follows. The details on the circuit design and the SET assessment of the majority voter architectures are discussed in Section 2. Section 3 presents and discusses the results. Section 4 summarizes this work.

Section snippets

Circuit design and radiation sensitivity methodology

The four majority voter architectures shown in Fig. 2 were designed based on a commercial 65 nm bulk CMOS technology. In addition, they were designed to be compatible with the standard-cell library provided by the Product Design Kit (PDK). A fixed cell height is set to 13 tracks of the metal pitch, i.e. 2.6-μm high. To provide flexibility in the cell routing, intra-cell connections are primarily done using the metal 1 (M1), except for some cases in which metal 2 (M2) is used horizontally. The

Results and discussion

In this work, four majority voter architectures exploiting complex-gate and standard cells were designed based on a commercial 65 nm bulk CMOS technology. The maximum, mean and standard deviation of the SET pulse width distribution is shown in Fig. 4 when considering a particle LET of 78.23 MeV·cm2/mg. The lowest pulse widths are observed for both complex-gate MJV, the CMOS1 and CMOS2. This is attributed to the contribution of pulse quenching effect (PQE) inherent of inversion stages in

Conclusion

Redundancy-based hardening techniques are widely used to provide fault-tolerant systems. This work has evaluated the robustness of four majority voter architectures, which is the circuit that constitutes the critical point of failure in Triple-Modular Redundancy (TMR) methodologies. Also, a signal probability analysis is proposed as an optimization strategy for TMR block insertion algorithms. Despite the reduced layout design, complex-gate voter architectures have shown, on average, a higher

Declaration of competing interest

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Acknowledgments

This work was realized within RADSAGA project. The RADSAGA Innovative Training Network project has received funding from the European Union's Horizon 2020 research and innovation program under the Marie Skłodowska-Curie grant agreement number 721624.

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