Thermal performance analysis of GaN nanowire and fin-shaped power transistors based on self-consistent electrothermal simulations
Introduction
Excellent performance of gallium nitride (GaN)-based transistors concerning breakdown voltage, on-resistance, and switching speed has made them a promising candidate for power electronic applications [1]. Although lateral GaN transistors are commercially available today, vertical structures are more desired for applications where high voltage and current levels are required [2]. Two main architectures are currently followed for GaN vertical power transistors: fin field-effect transistor (FinFET) [3] and nanowire-based field-effect transistor (NWFET) [4]. These two types of structures, which are both able to exhibit enhancement-mode operation, have offered significant results. For the FinFET structures, low on-resistances with blocking voltages of 800 V were presented [3], while the feasibility of a further increase in the value of the breakdown voltage has been recently shown [5]. It has been demonstrated that the wrap-around gate structure of the NWFETs provides the optimum electrostatic control in transistor design [6], but still a breakdown voltage of only 140 V could be achieved from these transistors [4]. However, TCAD simulations have shown the possibility of designing very low on-resistance NWFETs with breakdown voltages above 900 V [7].
Despite the ability of handling large currents and high voltages, severe self-heating can strongly limit the maximum achievable power density from these power transistors [8]. In fact, the high channel temperature induced by self-heating affects device reliability and might lead to sudden and destructive burnout [9]. Hence, a solid understanding of heat generation and dissipation as well as the impact of the possible thermal management techniques is essential. A comprehensive electrothermal study of GaN vertical FinFETs indicated better thermal performance of them compared to lateral devices [10]. Although electrical characteristics of GaN NWFETs have been studied extensively [7,11], thermal behavior of these devices still needs a detailed analysis. Therefore, in this paper, we present 2-D electrothermal simulations of a GaN NWFET validated by experimental data. To obtain a comparative assessment for the thermal performance of the nanowire architecture, we also simulate a FinFET structure with the same sizes. 3-D thermal simulations of FinFET devices by considering realistic back-end-of-line (BEOL) structures have shown that most of the heat flows out through the interconnect metals [12,13]. Thus, we account for the heat removal from the interconnects by using external lumped thermal resistances for the metal contacts. This analysis will also comment on the usage of the drain contact on top of the NWFETs, which is opposite to the proposed Fin-structures. Finally, the impact of changing the thermal surface resistance of the top contact and the substrate thickness is further discussed as the determining factors for the heat flux coming out of the GaN vertical power transistors.
Section snippets
Electrothermal study of GaN NWFET and FinFET structures
To perform self-consistent electrothermal simulations, a hydrodynamic model for electron transport and the standard drift-diffusion model for holes coupled with the Poisson and temperature equations were solved using Synopsys Sentaurus Device Simulator [14]. Since high-energy electrons in the channel of transistors do not follow an equilibrium Fermi-Dirac distribution, it is necessary to solve an energy flux equation for electrons in order to account for velocity overshoot effects [15]. For
Results and discussion
The simulated DC I-V characteristics of the NWFET is shown in Fig. 3 (a) in comparison to experimental data. The current decrease due to self-heating is in a very good agreement with our measurement results. Fig. 3 (b) shows the simulated I-V characteristics of the FinFET, which was designed as the isometric counterpart of the NWFET. Fig. 4 shows the lattice temperature distributions of the NWFET and FinFET in the active region at two different bias conditions resulting in almost the same peak
Conclusion
We have presented self-consistent electrothermal simulations of GaN NWFETs and vertical FinFETs to investigate their thermal performance. It was shown that the peak temperature in the NWFET is close to the top drain contact, while it is located on top of the substrate region in the FinFET. This difference makes heat removal from the top contact easier for the NWFET. Thus, reducing the thermal resistance of the contacts has a larger impact on improving thermal performance of the NWFET than the
Acknowledgment
The research leading to these results has received funding from the German Research Foundation (DFG) within the project “3D concepts for gallium nitride electronics”.
References (31)
- et al.
Electro-thermal modeling of multifinger AlGaN/GaN HEMT device operation including thermal substrate effects
Microelectron. Reliab.
(2008) - et al.
A review of the use of electro-thermal simulations for the analysis of heterostructure FETs
Microelectron. Reliab.
(2007) - et al.
Performance analysis and simulation of vertical gallium nitride nanowire transistors
Solid State Electron.
(2018) - et al.
AlGaN/GaN HEMTs: experiment and simulation of DC characteristics
Solid State Electron.
(2006) - et al.
Three-dimensional finite-element thermal simulation of GaN-based HEMTs
Microelectron. Reliab.
(2009) - et al.
Normally off vertical 3-D GaN nanowire MOSFETs with inverted p-GaN channel
IEEE Trans. Electron Devices
(2018) - et al.
In-depth analysis and modelling of self-heating effects in nanometric DGMOSFETs
Solid State Electron.
(2013) - et al.
GaN power transistors on Si substrates for switching applications
Proc. IEEE
(2010) - et al.
Power devices on bulk gallium nitride substrates: an overview of ARPA-E's SWITCHES program
- et al.
High-performance GaN vertical fin power transistors on bulk GaN substrates
IEEE Electron Device Lett.
(2017)
Vertical architecture for enhancement mode power transistors based on GaN nanowires
Appl. Phys. Lett.
1200 V GaN vertical fin power field-effect transistors
GaN Nanowire MOSFET With near-ideal subthreshold slope
IEEE Electron Device Lett.
Simulation study of high voltage vertical GaN nanowire field effect transistors
ECS Trans.
Electrothermal simulation and thermal performance study of GaN vertical and lateral power transistors
IEEE Trans. Electron Devices
Cited by (2)
3D GaN nanoarchitecture for field-effect transistors
2019, Micro and Nano EngineeringCitation Excerpt :3D FETs with both depletion mode (D-mode) and E-mode operation were reported with threshold voltages ranging between −30 V and 2.5 V. Finally, as known from modern Si MOSFETs [18], multigate technologies such as wrap-around gates for NWs or trigates for NFs can efficiently improve the electrostatic channel control, resulting in a very low subthreshold swing (SS) and reduced short channel effects [19]. Moreover, nanostructures can improve both the linearity [99,141,149] and thermal performance [138,140] of transistors, as will be discussed later. These potential advantages suggest that GaN nanostructures should be considered for future transistor technology.