Diagnosis of a soft short and local variations of parameters occurring simultaneously in analog CMOS circuits
Introduction
Fault diagnosis of analog circuits is an important and still open problem for design validation of electronic devices [1], [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23]. Generally, fault diagnosis includes detection of faulty circuits, location of faulty elements, and evaluation of their parameters.
The majority of defects that are met in production, inspection, and operation are local spot defects. They take forms of splotches of missing or extra material and can cause electrical faults, among them the most common are shorts and opens [12]. These faults are classified as catastrophic or hard if they constitute the ideal shorts or opens in the circuit connectivity. Incomplete short or open in the circuit connectivity are classified as soft defects. The soft defects can be modeled by resistors. The resistance of soft open defects can vary from less than 100 kΩ to several GΩ, whereas the resistance of soft short defects can reach several kΩ, [5], [6], [11], [12]. Shorts constitute the majority of the spot defects and they are the dominant cause of failures in modern CMOS circuits. In consequence most research has focused on them. A soft short defect is unintended connection between two otherwise unconnected nodes by a resistor of non–negligible resistance. Often it is referred to as bridge. During the last years a number of works were focused on spot defect diagnosis in analog circuits [6], [7], [10], [11], [19], [20]. Reference [6] presents a method for diagnosis of local spot defects using the fault dictionary approach. The method aims to find a subset of defects that are the most likely to have occurred. Reference [11] is devoted to open defects and shows that they can cause a circuit to function poorly. In reference [19] a diagnostic method that allows detecting, locating and estimating the value of the soft spot defect in circuits with possible multiple operating points is developed. The method is based on the theory named a linear complementarity problem, leading to characteristics that simulate the defects in terms of some measured voltages. Reference [20] brings a method for diagnosis of soft shorts, mainly in BJT circuits, considering the thermal behavior of the chip.
Parameter variations in ICs are due to global manufacturing variations or due to local random fluctuations. In current CMOS technology the global variations of parameters are measured by dedicated test structures included in the wafer. The local variations affect the components across the die independently [6]. The examples include local geometrical deformations such as variations in the channel length L and width W, the oxide thickness TOX, the threshold voltage Vt etc. For short channel transistors Vt is predominantly determined by the transistors geometries, in particular Leff [12]. Channel width is usually considerably larger than channel length and, as a rule, its variations are relatively small and may be neglected. The problem of diagnosing of parameter variations is discussed in several papers [16], [17], [21]. In reference [16] an approach has been proposed leading to the actual parameter values. It is based on the homotopy concept with the simplicial method used as a tool to trace the homotopy path. An extended systematic search method for diagnosis of parametric variations in BJT and CMOS circuits is developed in [17]. Reference [21] offers a method for diagnosis of local variation of parameters in CMOS circuits designed in nanometer technology, based on Nelder-Mead optimization method.
In this paper a single soft short defect and local variations of parameters, occurring simultaneously are diagnosed in CMOS circuits designed in nanometer technology. Considering the short defect together with local parametric variations and taking into account the possibility of existing several solutions of the test equations make the diagnostic method reliable. The MOS transistors are characterized by BSIM 4.6 model and the local variations of the parameters: channel gate length L and oxide thickness TOX are considered separately for n and p-channel transistors. Their variations affect another MOS parameters which depend on L and TOX. The method developed in this paper allows diagnosing a single soft short from among msc potential shorts of this type, as well as the mentioned–above local variations of the parameters occurring simultaneously. Soft short will be simulated by a resistor RSC = 100xn, where xn is a relative parameter that is determined in the diagnostic process. The BSIM 4.6 model uses the parameter XL to correct channel length due to mask/etch effect Ldrawn = Lnom + XL. The deviation of L defined by the process corners is labeled DXL. Consequently, the channel length can be specified by the equation L = Ldrawn + (1 − xL)DXL, where xL is an auxiliary relative parameter [16]. At xL = 1, L = Ldrawn whereas at xL = 0, L = Ldrawn + DXL. The oxide thickness TOX can be specified by the equation TOX = TOXnom + (1 − xT)DTOX, where DTOX is the deviation of TOX defined for the process corners and xT is a relative parameter [16].
Section snippets
Preliminaries
To diagnose variations of n − 1 parameters and one soft short defect, specified by n relative parameters x1 , … , xn, two diagnostic tests are arranged similarly as in [15], [16], [21]. The first test, labeled A, is performed as shown in Fig. 1. The power supply voltage sources vs(1) , … , vs(q) are applied at q nodes accessible for excitation and the output voltages v1 , … , vm are measured at m nodes accessible for measurement.
We choose l sets of the input voltages {vs(1), …, vs(q)} i, i = 1 , … , l, and read lm
Proposed algorithm
To identify the actual soft short defect in the circuit, from among a set of potential defects of this type, some preliminary simulations are performed. We analyse the short –free circuit and msc circuits, each comprising 100 Ω resistor connected to the pair of points where the short defect is expected. In any case the parameters are assumed to be drawn in the case of L or nominal in the case of TOX. At first the simulations are carried out using the input voltages as in test A and the output
Numerical example
The proposed algorithm has been tested numerically using CMOS circuits. To illustrate effectiveness of the algorithm we consider the rail–to–rail input buffer [26] shown in Fig. 5, designed in nanometer technology. The transistors are characterized by the BSIM 4.6 model implemented in IsSPICE 4, Level 14 [25]. The nominal values of the channel lengths of the transistors are indicated in Fig. 5, whereas the nominal values of the oxide thicknesses of p-MOS and n-MOS transistors are (TOX)p = (TOX)n =
Conclusions
The reliable fault diagnosis method developed in this paper is dedicated to CMOS circuits designed in nanometer technology. The method allows diagnosing a single soft short and local variations of parameters, occurring simultaneously. It exploits test equations obtained on the basis of measurements at a limited number of points. Although these equations cannot be presented in explicit analytical form and may be satisfied by several sets of the relative parameters the method allows finding the
Acknowledgement
This work was supported by the Statutory Activities of Lodz University of Technology 501/12-12/1/5417.
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