Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress
Introduction
Remote-plasma-enhanced CVD (RPECVD) oxide/nitride (O/N) gate dielectric has been proposed as a near term gate dielectric candidate to replace the conventional gate oxide for advanced CMOS technologies. It is attributed to the fact that O/N stack dielectric possesses relatively high dielectric constant and low interface charge density, and is relatively easy for the integration of the fabrication process. Extensive investigations on the physical and electrical properties of RPECVD gate stacks have been reported [1], [2], [3]. It has been demonstrated that ultrathin RPECVD O/N gate dielectric with interface nitridation exhibits significant improvements in direct tunneling current, boron penetration, flatband voltage shift and channel mobility [2], [3]. The effect of interface nitridation on dielectric breakdown has been investigated. It was shown that interface nitridation, which incorporating monolayer nitrogen at the Si/SiO2 interface to reduce dangling bonds and interfacial strain relaxation [1]. As a result, the precursor density and the strained bonds are reduced, leading to the improvements in the dielectric breakdown such as gate leakage current, SILC and gate-drain hole tunneling [4]. Furthermore, it has been found in previous work [4], [5] that the hole trapping is created in the PMOSFETs with ultrathin RPECVD O/N dielectric under electrical stresses regardless of bias polarity.
Aside from increased tunneling leakage current, time-dependent dielectric breakdown (TDDB) is of increasing reliability concern and becomes another limiting factor for oxide scaling and power dissipation in deep-submicron semiconductor devices [6], [7]. The occurrence of TDDB is believed to ascribe to the formation of a percolation path between anode and cathode electrodes [8]. It has been revealed that TDDB lifetime is degraded at elevated temperatures due to the weaken oxide resistance to the hole transportation [9], increased trap generation rate and a lowering of Si/SiO2 barrier height [10]. A wide range of activation energies from 0.2 to 0.4 eV has been reported [11], which is dependent of the dielectric quality [11], oxide thickness [9], [10], temperature range, and the stress voltage [10], [11]. It was predicted that TDDB reliability may limit the scaling of oxide thickness to ∼2.2 nm for a 1 V operating voltage at room temperature [12], and 3.4 nm for 2.5 V at 125 °C [9]. It has been suggested that the reliability of most future devices should be tested for 125 °C [7].
This paper will focus on the investigation of the voltage and temperature dependence on reliability of ultrathin RPECVD O/N gate dielectric by using the accelerated TDDB test. The activation energy is determined from the Arrhenius plot over a wide range of temperatures, and it can be used to predict the TDDB lifetime between 25 and 125 °C at different stress voltages. Additionally, a 10-year lifetime is projected including effects of temperature acceleration, specified low cumulative failure rate and gate area scaling using the Weibull plot. The maximum operating voltage for the 2.07 nm O/N gate dielectric based on a 10-year lifetime with 0.01% failure rate and total gate area of 0.1 cm2 at 125 °C is projected.
Section snippets
Experimental
Devices were fabricated on 0.02–0.05 Ω cm 〈1 0 0〉 n-type silicon substrates using standard CMOS process. The deposition procedures of stacked O/N gate dielectric with plasma interface nitridation have been described in detail elsewhere [13]. The equivalent oxide thickness (EOT) of 2.07 nm was determined from high-frequency C–V curve with quantum mechanical correction [14]. An HP4155B semiconductor parameter analyzer was used to perform constant voltage stress (CVS) on the p+-poly/n-Si capacitors
Breakdown behavior and Weibull failure distributions
Fig. 1 shows the time evolution of the gate current for 2.07 nm RPECVD O/N gate dielectric during CVS at 25 °C. In CVS, soft breakdown characteristic shows gate fluctuation, which is attributed to the generation of charge trapping–detrapping at the local percolation paths. In other words, during the stress, the injected holes attack the O vacancy [15] and create a large number of broken Si–O and H–O bonds. Prior to the final stage of breakdown, the critical defect density of O/N gate dielectric
Temperature acceleration and activation energy
It is widely accepted that higher temperatures degrade TDDB reliability, and a wide range of thermal activation energies has been reported to be a function of applied electric field, oxide thickness and temperature range [11]. For thicker oxides (>6.5 nm), temperature dependence of field acceleration factor has been reported [22]. This strong temperature dependence may be due to the fact that the effective defect size increases at higher temperature [7], [10]. However, for thinner oxides, other
Device lifetime projection by TBBD reliability
In this section, the conventional voltage and temperature acceleration models are used to predict the TDDB lifetime at elevated temperature, low voltage and low percentile failure rate. Fig. 6 shows the time evolution of gate current for various gate areas, at which the time-to-HBD can be determined. There is a consensus that the breakdown spots are randomly created through the oxide according to a Poisson distribution as given below [25], [26]Combining Eqs. , ,
Conclusions
In this work, the voltage and temperature dependence on reliability for ultrathin RPECVD O/N gate dielectric was investigated. There are no statistically significant differences in the values of the Weibull shape factor (=1.9) for different stress voltages and temperatures. This observation implies that the breakdown mechanisms are the same in the investigated range. QBD is reduced at higher stress voltages due to the higher defect generation rate. The activation energy of 0.39 eV is determined
References (30)
- et al.
Improvement of gate dielectric reliability for p+poly MOS devices using remote PECVD top nitride deposition on ultra-thin (2.4–6 nm) gate oxides
Microelectron. Reliab.
(1999) - et al.
Structural dependence of breakdown characteristics and electrical degradation in ultrathin RPECVD oxide/nitride gate dielectrics under constant voltage stress
Solid State Electron.
(2003) - et al.
Oxide scaling limit for future logic and memory technology
Microelectron. Eng.
(1999) - et al.
Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics
Microelectron. Reliab.
(2001) - et al.
Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides
Solid State Electron.
(2002) - et al.
Electric field dependence of TDDB activation energy in ultra-thin oxides
Microelectron. Reliab.
(1996) Ultrathin nitrided gate dielectrics: plasma processing, chemical characterization, performance, and reliability
IBM J. Res. Develop.
(1999)- et al.
The performance and reliability of PMOSFET’s with ultrathin silicon nitride/oxide stacked gate dielectrics with nitrided Si–SiO2 interfaces prepared by remote enhanced CVD and post-deposition rapid thermal annealing
IEEE Trans. Electron Dev.
(2000) - Lee YM, Wu Y, Hong J, Lucovsky G. Degradation and SILC effects of RPECVD sub-2.0 nm oxide/nitride (O/N) and oxynitride...
Ultrathin gate oxide reliability: physical models, statistics, and characterization
IEEE Trans. Electron Dev.
(2002)
Non-Arrhenius temperature dependence of reliability in ultrathin silicon dioxide films
Appl. Phys. Lett.
Percolation models for gate oxide breakdown
J. Appl. Phys.
Effects of temperature and defects on breakdown lifetime of thin SiO2 at very low voltages
IEEE Int. Reliab. Phys. Symp. Proc.
Investigation of temperature acceleration of thin oxide time-to-breakdown
Microelectron. Eng.
Temperature acceleration of time-dependent dielectric breakdown
IEEE Trans. Electron Dev.
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