Breakdown and reliability of p-MOS devices with stacked RPECVD oxide/nitride gate dielectric under constant voltage stress

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Abstract

In this work, the effects of voltage and temperature on the TDDB characteristics of ∼2.0 nm stacked oxide/nitride (O/N) dielectric, prepared by remote plasma enhanced CVD (RPECVD), has been investigated. The breakdown characteristics and time-to-breakdown (tBD) are recorded from p+-poly/n-Si capacitors under constant voltage stress (CVS) at different temperatures. The tBD cumulative distributions exhibit a single Weibull slope β of ∼1.9 for different applied voltages. The charge-to-breakdown (QBD) is integrated from the gate current as a function of stress times, and can be used to extract the defect generation rate. The activation energy of 0.39 eV is determined from the Arrhenius law, and the average temperature acceleration factor is about 45 between 25 and 125 °C for a constant gate voltage. The extrapolation of the TDDB lifetime with low percentile failure rate of 0.01% provides a 10-year projection for a total gate area of 0.1 cm2 on a chip at 125 °C with the Poisson area-scaling law and a constant voltage acceleration factor of ∼14.83 V−1. It is projected that the maximum safe operating voltage is ∼1.9 V for 2.07 nm O/N gate dielectric.

Introduction

Remote-plasma-enhanced CVD (RPECVD) oxide/nitride (O/N) gate dielectric has been proposed as a near term gate dielectric candidate to replace the conventional gate oxide for advanced CMOS technologies. It is attributed to the fact that O/N stack dielectric possesses relatively high dielectric constant and low interface charge density, and is relatively easy for the integration of the fabrication process. Extensive investigations on the physical and electrical properties of RPECVD gate stacks have been reported [1], [2], [3]. It has been demonstrated that ultrathin RPECVD O/N gate dielectric with interface nitridation exhibits significant improvements in direct tunneling current, boron penetration, flatband voltage shift and channel mobility [2], [3]. The effect of interface nitridation on dielectric breakdown has been investigated. It was shown that interface nitridation, which incorporating monolayer nitrogen at the Si/SiO2 interface to reduce dangling bonds and interfacial strain relaxation [1]. As a result, the precursor density and the strained bonds are reduced, leading to the improvements in the dielectric breakdown such as gate leakage current, SILC and gate-drain hole tunneling [4]. Furthermore, it has been found in previous work [4], [5] that the hole trapping is created in the PMOSFETs with ultrathin RPECVD O/N dielectric under electrical stresses regardless of bias polarity.

Aside from increased tunneling leakage current, time-dependent dielectric breakdown (TDDB) is of increasing reliability concern and becomes another limiting factor for oxide scaling and power dissipation in deep-submicron semiconductor devices [6], [7]. The occurrence of TDDB is believed to ascribe to the formation of a percolation path between anode and cathode electrodes [8]. It has been revealed that TDDB lifetime is degraded at elevated temperatures due to the weaken oxide resistance to the hole transportation [9], increased trap generation rate and a lowering of Si/SiO2 barrier height [10]. A wide range of activation energies from 0.2 to 0.4 eV has been reported [11], which is dependent of the dielectric quality [11], oxide thickness [9], [10], temperature range, and the stress voltage [10], [11]. It was predicted that TDDB reliability may limit the scaling of oxide thickness to ∼2.2 nm for a 1 V operating voltage at room temperature [12], and 3.4 nm for 2.5 V at 125 °C [9]. It has been suggested that the reliability of most future devices should be tested for 125 °C [7].

This paper will focus on the investigation of the voltage and temperature dependence on reliability of ultrathin RPECVD O/N gate dielectric by using the accelerated TDDB test. The activation energy is determined from the Arrhenius plot over a wide range of temperatures, and it can be used to predict the TDDB lifetime between 25 and 125 °C at different stress voltages. Additionally, a 10-year lifetime is projected including effects of temperature acceleration, specified low cumulative failure rate and gate area scaling using the Weibull plot. The maximum operating voltage for the 2.07 nm O/N gate dielectric based on a 10-year lifetime with 0.01% failure rate and total gate area of 0.1 cm2 at 125 °C is projected.

Section snippets

Experimental

Devices were fabricated on 0.02–0.05 Ω cm 〈1 0 0〉 n-type silicon substrates using standard CMOS process. The deposition procedures of stacked O/N gate dielectric with plasma interface nitridation have been described in detail elsewhere [13]. The equivalent oxide thickness (EOT) of 2.07 nm was determined from high-frequency CV curve with quantum mechanical correction [14]. An HP4155B semiconductor parameter analyzer was used to perform constant voltage stress (CVS) on the p+-poly/n-Si capacitors

Breakdown behavior and Weibull failure distributions

Fig. 1 shows the time evolution of the gate current for 2.07 nm RPECVD O/N gate dielectric during CVS at 25 °C. In CVS, soft breakdown characteristic shows gate fluctuation, which is attributed to the generation of charge trapping–detrapping at the local percolation paths. In other words, during the stress, the injected holes attack the O vacancy [15] and create a large number of broken Si–O and H–O bonds. Prior to the final stage of breakdown, the critical defect density of O/N gate dielectric

Temperature acceleration and activation energy

It is widely accepted that higher temperatures degrade TDDB reliability, and a wide range of thermal activation energies has been reported to be a function of applied electric field, oxide thickness and temperature range [11]. For thicker oxides (>6.5 nm), temperature dependence of field acceleration factor has been reported [22]. This strong temperature dependence may be due to the fact that the effective defect size increases at higher temperature [7], [10]. However, for thinner oxides, other

Device lifetime projection by TBBD reliability

In this section, the conventional voltage and temperature acceleration models are used to predict the TDDB lifetime at elevated temperature, low voltage and low percentile failure rate. Fig. 6 shows the time evolution of gate current for various gate areas, at which the time-to-HBD can be determined. There is a consensus that the breakdown spots are randomly created through the oxide according to a Poisson distribution as given below [25], [26]ln[−ln(1−F)]−ln[−ln(1−Fα)]=lnAAαCombining Eqs. , ,

Conclusions

In this work, the voltage and temperature dependence on reliability for ultrathin RPECVD O/N gate dielectric was investigated. There are no statistically significant differences in the values of the Weibull shape factor (=1.9) for different stress voltages and temperatures. This observation implies that the breakdown mechanisms are the same in the investigated range. QBD is reduced at higher stress voltages due to the higher defect generation rate. The activation energy of 0.39 eV is determined

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