Background analog and mixed signal calibration system for time-interleaved ADC

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Abstract

In this work, a novel background calibration technique for time-interleaved analog-to-digital converters (ADCs) is proposed. The offset, gain, time skew and bandwidth mismatches are considered and analyzed in detail, highlighting the efficiency of the proposed calibration method. The calibration system is an analog mixed one where the error detection is performed digitally by three detectors: offset detector, amplitude detector and phase detector. The correction is performed in both the analog and the digital domains. We have proposed a calibration sequence that allows us to distinguish between the different errors, resulting in high accuracy detection and correction phases. The efficiency and the accuracy of the calibration technique are verified through MATLAB® and VHDL-AMS simulations.

Introduction

Modern communication system applications emphasize the need for faster, higher resolution, analog-to-digital converters (ADCs) than those commercially available. These applications do not only require faster ADC but also need large dynamic range and low distortion. The ADC is the interface between the analog front-end and the digital core of any communication system. The continuously expanding demand for high speeds and data throughput in communication systems imposes challenging requirements on the speed and resolution of the ADC.

Aside from communication systems, a multitude of other applications requires such capabilities from an ADC. Digital sampling oscilloscope as well as laser imaging systems are two notable examples, where the resolution of the latter is improved by increasing its sampling frequency. Such applications require a bandwidth (BW) up to GHz-frequencies and over 10-bit resolution. This cannot be achieved by conventional ADC with moderate power consumption [1].

The time-interleaved ADC (TIADC) that was introduced in the 1980 [2], enables the construction of a high speed converter using multiple low speed ones. Conventional ADCs such as pipeline ADC or successive approximation ADC (SAR ADC) can be used as the low-speed converters in the TIADC. The TIADC consists of M parallel channels. Each channel contains the low-speed ADC. The channels operate at the same sampling frequency fADC but with different phases, the phase shift between each two consecutive clocks is constant and equals 2π/M as shown in Fig. 1. Using the clock scheme (Fig. 1), the input will be uniformly sampled by each of the low-speed ADCs. The output data rate of the whole system fs is M times faster than the low-speed ADC. The TIADC is a Nyquist type data converter, thus its bandwidth equals half of the sampling frequency.

Mismatches between the ADCs represent a major issue for the TIADC and result in severe performance degradation. Spurious free dynamic range (SFDR) is reduced as a result of such mismatches. Signal-to-noise and distortion ratio (SNDR) is also reduced, which directly reduces the effective number of bits of the TIADC. Different types of mismatches are found in this system such as offset mismatch, gain mismatch, time skew mismatch and bandwidth mismatch.

This work targets the calibration of an 800 MS/s, 4-channel, 12-bit TIADC suffering from all four types of mismatches combined. The goal is to construct a calibration system that scales seamlessly to higher sampling rates, without complex digital algorithm or analog circuits limitations. The effect of the harmonic distortion and the thermal noise on the calibration efficiency will be considered.

This paper is organized as follows: first, in Section 2, the different mismatches are analyzed in order to understand their effects on the performances. Then in Section 3, the proposed calibration technique is presented. Section 4 shows the sequence that should be used in order to calibrate the TIADC. The efficiency of the calibration system is assessed through system-level simulation in Section 5 and finally, Section 6 concludes the paper.

Section snippets

Offset mismatch

The effect of offset mismatch between the ADCs can be evaluated by considering the case of a DC input signal to the TIADC, where each low-speed ADC has different offset error. In this case, the output code from each channel may be different. In fact the combined TIADC output will be periodic with frequency fs/M. Assuming a sinusoidal input voltage Vin of the form:Vin=Asin(2πfint+ϕin)the output of the ith channel Vouti is given byVouti(n)=Voffi+Asin(2πfin[nMTs+(i1)Ts]+ϕin)where Vouti is the

Proposed background calibration technique

The calibration is used in order to decrease the impact of the presented mismatches on the TIADC performances. The foreground calibration mode interrupts the normal operation of the TIADC and the calibration is performed offline [9]. The errors are extracted from a known calibration signal [10]. This mode is suitable for measurement application where the user can interrupt his measurements in order to calibrate the TIADC [9]. Its main inconvenience is that it does not account for the supply and

TIADC calibration sequence

As mentioned before, the detection of each type of mismatches is affected by the other mismatches. Our proposed calibration technique has 2 features that can be used to distinguish between the different types of mismatches: the calibration signal frequency used and the calibration sequence. The choice of fcal is critical because the bandwidth mismatch generates a dynamic gain mismatch. For high fcal, the detected amplitude will be affected by both the gain and the bandwidth mismatches. Thus,

System model and results

A 4-channel, 12-bit, 800 MS/s TIADC is modelled using MATLAB® with the calibration system proposed in Section 3 to validate the concept. The calibration system can be also used for higher sampling rate TIADC. In Table 1, different parameters of the TIADC model are listed. Due to the frequency dependent errors, the input signal frequency fin is chosen to be high, near half the Nyquist frequency. The system non-idealities such as the ADC harmonic distortion, thermal noise and clock jitter are not

Conclusion

We have presented a fast background analog-mixed signal calibration technique for the TIADC. The novel background technique used in the calibration system is based on an extra ADC and multiplexing in the S/Hs architecture to easily apply the calibration signal. The detection of the different errors is performed in the digital domain and depends on three main parts: the offset, the amplitude and the phase detectors. The correction is performed in both analog and digital domains. The time skew

Acknowledgements

This work is funded by French Research Program NANO-2012 in cooperation with STMicroelectronics R&D Team, Grenoble.

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